1: Disables DMA and all of the service
interrupts.
BITS [2:0] Parallel Port DMA (read-only)
Refer to Table 44C.
0: Enables one of the following 3 cases of
interrupts. Once one of the
3 service
ecr (Extended Control Register)
ADDRESS OFFSET = 402H
Mode = all
This register controls the extended ECP parallel
port functions.
interrupts has occurred serviceIntr bit shall be
set to a 1 by hardware. It must be reset to 0 to
re-enable the interrupts. Writing this bit to a 1
will not cause an interrupt.
case dmaEn=1:
BITS 7,6,5
During DMA (this bit is set to a 1 when
terminal count is reached).
case dmaEn=0 direction=0:
These bits are Read/Write and select the Mode.
BIT 4 nErrIntrEn
Read/Write (Valid only in ECP Mode)
1: Disables the interrupt generated on the
asserting edge of nFault.
0: Enables an interrupt pulse on the high to low
edge of nFault. Note that an interrupt will be
generated if nFault is asserted (interrupting)
and this bit is written from a 1 to a 0. This
prevents interrupts from being lost in the time
between the read of the ecr and the write of
the ecr.
BIT 3 dmaEn
Read/Write
1: Enables DMA (DMA starts when serviceIntr is
0).
0: Disables DMA unconditionally.
BIT 2 serviceIntr
This bit shall be set to 1 whenever there are
writeIntrThreshold or more bytes free in the
FIFO.
case dmaEn=0 direction=1:
This bit shall be set to 1 whenever there are
readIntrThreshold or more valid bytes to be
read from the FIFO.
BIT 1 full
Read only
1: The FIFO cannot accept another byte or the
FIFO is completely full.
0: The FIFO has at least 1 free byte.
BIT 0 empty
Read only
1: The FIFO is completely empty.
0: The FIFO contains at least 1 byte of data.
Read/Write
102
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