t1
t2
t2
CLOCKI
FIGURE 7A - INPUT CLOCK TIMING
DESCRIPTION MIN
NAME
TYP
70
MAX
UNITS
ns
t1
t2
t1
t2
Clock Cycle Time for 14.318MHZ
Clock High Time/Low Time for 14.318MHz
Clock Cycle Time for 32KHZ
35
ns
31.25
16.53
ms
Clock High Time/Low Time for 32KHz
Clock Rise Time/Fall Time (not shown)
ms
5
ns
FIGURE 7B - RESET TIMING
t4
RESET_DRV
NAME
DESCRIPTION
RESET width (Note 1)
MIN
TYP MAX
UNITS
t4
1.5
ms
Note 1: The RESET width is dependent upon the processor clock. The RESET must be active while
the clock is running and stable.
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