Table 64 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08]
NAME
REG
DEFINITION
STATE
INDEX
Force Change 0 is cleared on nSTEP and nDS0
DSKCHG (FDC DIR Register, Bit 7) = (nDS0 AND
Force Change 0) OR nDSKCHG
Bit[0] Data Rate Select 0
Bit[1] Data Rate Select 1
Bit[2] PRECOMP 0
Floppy Data Rate
Select Shadow
0xC2
(R)
C
Bit[3] PRECOMP 1
Bit[4] PRECOMP 2
Bit[5] Reserved
Bit[6] Power Down
Bit[7] Soft Reset
UART1 FIFO
Control Shadow
0xC3
0xC4
Bit[0] FIFO Enable
C
C
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
Bit[3] DMA Mode Select
Bit[5:4] Reserved
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
Bit[0] FIFO Enable
UART2 FIFO
Control Shadow
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
Bit[3] DMA Mode Select
Bit[5:4] Reserved
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
Bit[0] PME_En
= 0 nPME signal assertion is disabled (default)
= 1 Enables FDC37B77x to assert nPME signal
Bit[7:1] Reserved
PME Control
Default = 0x00 on
VTR POR
0xC5
(R/W)
PME_En is not affected by Vcc POR, SOFT RESET
or HARD RESET
PME Status
Default = 0x00 on
POR VTR
0xC6
Bit[0] PME_Status
(R/w Clear) = 0 (default)
= 1 Set when FDC37B77x would normally assert the
PCI nPME signal, independent of the state of the
PME_En bit.
Bit[7:1] Reserved
PME_Status is not affected by Vcc POR, SOFT
RESET or HARD RESET.
Writing a “1” to PME_Status will clear it and cause
the FDC37B77x to stop asserting nPME, in enabled.
154
SMSC [ SMSC CORPORATION ]
