SERIAL IRQ
The SMI is enabled onto the SMI frame of the Serial IRQ via bit 6 of SMI Enable Register 2.
SERIAL INTERRUPTS
The FDC37B77x will support the serial interrupt to transmit interrupt information to the host system.
The serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0.
Timing Diagrams For IRQSER Cycle
PCICLK = 33Mhz_IN pin
IRQSER = SIRQ pin
A) Start Frame timing with source sampled a low pulse on IRQ1
START FRAME
IRQ0 FRAME IRQ1 FRAME IRQ2 FRAME
SL
or
H
R
T
S
R
T
S
R
T
S
R
T
H
PCICLK
START1
IRQSER
IRQ1 Host Controller
None
IRQ1
None
Drive Source
H=Host Control
R=Recovery
SL=Slave Control
T=Turn-around
S=Sample
1) Start Frame pulse can be 4-8 clocks wide.
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SMSC [ SMSC CORPORATION ]
