C. When a timeout interrupt has occurred it is
cleared and the timer reset when the CPU
reads one character from the RCVR FIFO.
FIFO INTERRUPT MODE OPERATION
When the RCVR FIFO and receiver interrupts are
enabled (FCR bit 0 = "1", IER bit 0 = "1"), RCVR
interrupts occur as follows:
D. When a timeout interrupt has not occurred the
timeout timer is reset after a new character is
received or after the CPU reads the RCVR
FIFO.
A. The receive data available interrupt will be
issued when the FIFO has reached its
programmed trigger level; it is cleared as soon
as the FIFO drops below its programmed
trigger level.
When the XMIT FIFO and transmitter interrupts
are enabled (FCR bit 0 = "1", IER bit 1 = "1"),
XMIT interrupts occur as follows:
B. The IIR receive data available indication also
occurs when the FIFO trigger level is reached.
It is cleared when the FIFO drops below the
trigger level.
A. The transmitter holding register interrupt (02H)
occurs when the XMIT FIFO is empty; it is
cleared as soon as the transmitter holding
register is written to (1 of 16 characters may be
written to the XMIT FIFO while servicing this
interrupt) or the IIR is read.
C. The receiver line status interrupt (IIR=06H), has
higher priority than the received data available
(IIR=04H) interrupt.
B. The transmitter FIFO empty indications will be
delayed 1 character time minus the last stop
bit time whenever the following occurs:
THRE=1 and there have not been at least two
bytes at the same time in the transmitter FIFO
since the last THRE=1. The transmitter
interrupt after changing FCR0 will be
immediate, if it is enabled.
D. The data ready bit (LSR bit 0) is set as soon as
a character is transferred from the shift register
to the RCVR FIFO. It is reset when the FIFO
is empty.
When RCVR FIFO and receiver interrupts are
enabled, RCVR FIFO timeout interrupts occur as
follows:
Character timeout and RCVR FIFO trigger level
interrupts have the same priority as the current
received data available interrupt; XMIT FIFO
empty has the same priority as the current
transmitter holding register empty interrupt.
A. A FIFO timeout interrupt occurs if all the
following conditions exist:
-
-
At least one character is in the FIFO.
The most recent serial character received
was longer than 4 continuous character times
ago. (If 2 stop bits are programmed, the
second one is included in this time delay).
The most recent CPU read of the FIFO was
longer than 4 continuous character times ago.
-
This will cause a maximum character received to
interrupt issued delay of 160 msec at 300 BAUD
with a 12 bit character.
B. Character times are calculated by using the
RCLK input for a clock signal (this makes the
delay proportional to the baudrate).
78
SMSC [ SMSC CORPORATION ]
