Table 34 - Baud Rates Using 1.8462 MHz Clock for <= 38.4K; Using 1.8432MHz Clock
for 115.2k ; Using 3.6864MHz Clock for 230.4k; Using 7.3728 MHz Clock for 460.8k
DESIRED
BAUD RATE
DIVISOR USED TO
GENERATE 16X CLOCK
PERCENT ERROR DIFFERENCE
HIGH
BETWEEN DESIRED AND ACTUAL1
SPEED BIT2
50
75
2304
1536
1047
857
768
384
192
96
0.001
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
-
110
-
134.5
150
0.004
-
300
-
600
-
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
57600
115200
230400
460800
-
64
-
58
0.005
48
-
32
-
-
24
16
-
12
-
6
-
3
0.030
0.16
0.16
0.16
0.16
2
1
32770
32769
1
Note1: The percentage error for all baud rates, except where indicated otherwise, is 0.2%.
Note 2: The High Speed bit is located in the Device Configuration Space.
Effect Of The Reset on Register File
The Reset Function Table (Table 35) details the effect of the Reset input on each of the registers of the
Serial Port.
77
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