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FDC37B72X_07 参数 Datasheet PDF下载

FDC37B72X_07图片预览
型号: FDC37B72X_07
PDF下载: 下载PDF文件 查看货源
内容描述: 128引脚增强型超级I / O控制器,支持ACPI [128 Pin Enhanced Super I/O Controller with ACPI Support]
分类和应用: 控制器
文件页数/大小: 238 页 / 816 K
品牌: SMSC [ SMSC CORPORATION ]
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data rate selected in the Data Rate Select  
Register. The user must ensure that these two  
data rates remain consistent.  
will be written in the Gap2 field for the 500 Kbps  
perpendicular mode (WGATE = 1, GAP =0).  
It should be noted that none of the alterations in  
Gap2 size, VCO timing, or Write Gate timing affect  
normal program flow. The information provided  
here is just for background purposes and is not  
The Gap2 and VCO timing requirements for  
perpendicular recording type drives are dictated by  
the design of the read/write head. In the design of  
this head, a pre-erase head precedes the normal  
read/write head by a distance of 200 micrometers.  
This works out to about 38 bytes at a 1 Mbps  
recording density. Whenever the write head is  
enabled by the Write Gate signal, the pre-erase  
head is also activated at the same time. Thus,  
when the write head is initially turned on, flux  
transitions recorded on the media for the first 38  
bytes will not be preconditioned with the pre-erase  
head since it has not yet been activated. To  
needed for normal operation.  
Once the  
Perpendicular Mode command is invoked, FDC  
software behavior from the user standpoint is  
unchanged.  
The perpendicular mode command is enhanced to  
allow specific drives to be designated  
Perpendicular recording drives. This enhancement  
allows data transfers between Conventional and  
Perpendicular drives without having to issue  
Perpendicular mode commands between the  
accesses of the different drive types, nor having to  
change write pre-compensation values.  
accommodate  
this  
head  
activation  
and  
deactivation time, the Gap2 field is expanded to a  
length of 41 bytes. The format field shown on  
Page 58 illustrates the change in the Gap2 field  
size for the perpendicular format.  
When both GAP and WGATE bits of the  
PERPENDICULAR MODE COMMAND are both  
programmed to "0" (Conventional mode), then D0,  
D1, D2, D3, and D4 can be programmed  
independently to "1" for that drive to be set  
automatically to Perpendicular mode. In this mode  
the following set of conditions also apply:  
1. The GAP2 written to a perpendicular drive  
during a write operation will depend upon the  
programmed data rate.  
On the read back by the FDC, the controller must  
begin synchronization at the beginning of the sync  
field. For the conventional mode, the internal PLL  
VCO is enabled (VCOEN) approximately 24 bytes  
from the start of the Gap2 field. But, when the  
controller operates in the 1 Mbps perpendicular  
mode (WGATE = 1, GAP = 1), VCOEN goes  
active after 43 bytes to accommodate the  
increased Gap2 field size. For both cases, and  
approximate two-byte cushion is maintained from  
the beginning of the sync field for the purposes of  
avoiding write splices in the presence of motor  
speed variation.  
2. The write pre-compensation given to  
perpendicular mode drive will be 0ns.  
a
3. For D0-D3 programmed to "0" for conventional  
mode drives any data written will be at the  
currently programmed write pre-compensation.  
For the Write Data case, the FDC activates Write  
Gate at the beginning of the sync field under the  
conventional mode. The controller then writes a  
new sync field, data address mark, data field, and  
CRC as shown on page 57. With the pre-erase  
head of the perpendicular drive, the write head  
must be activated in the Gap2 field to insure a  
proper write of the new sync field. For the 1 Mbps  
perpendicular mode (WGATE = 1, GAP = 1), 38  
bytes will be written in the Gap2 space. Since the  
bit density is proportional to the data rate, 19 bytes  
Note: Bits D0-D3 can only be overwritten when  
OW is programmed as a "1".If either GAP or  
WGATE is a "1" then D0-D3 are ignored.  
Software and hardware resets have the following  
effect on the PERPENDICULAR MODE  
COMMAND:  
1. "Software" resets (via the DOR or DSR  
registers) will only clear GAP and WGATE bits  
to "0". D0-D3 are unaffected and retain their  
previous value.  
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