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FDC37B72X_07 参数 Datasheet PDF下载

FDC37B72X_07图片预览
型号: FDC37B72X_07
PDF下载: 下载PDF文件 查看货源
内容描述: 128引脚增强型超级I / O控制器,支持ACPI [128 Pin Enhanced Super I/O Controller with ACPI Support]
分类和应用: 控制器
文件页数/大小: 238 页 / 816 K
品牌: SMSC [ SMSC CORPORATION ]
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SYMBOL  
SC  
NAME  
DESCRIPTION  
Number of Sectors The number of sectors per track to be initialized by the Format  
Per Track  
Skip Flag  
command. The number of sectors per track to be verified during a  
Verify command when EC is set.  
SK  
When set to 1, sectors containing a deleted data address mark will  
automatically be skipped during the execution of Read Data. If Read  
Deleted is executed, only sectors with a deleted address mark will be  
accessed. When set to "0", the sector is read or written the same as  
the read and write commands.  
SRT  
Step Rate Interval The time interval between step pulses issued by the FDC.  
Programmable from 0.5 to 8 milliseconds in increments of 0.5 ms at  
the 1 Mbit data rate. Refer to the SPECIFY command for actual  
delays.  
ST0  
ST1  
ST2  
ST3  
Status 0  
Status 1  
Status 2  
Status 3  
Write Gate  
Registers within the FDC which store status information after a  
command has been executed. This status information is available to  
the host during the result phase after command execution.  
WGATE  
Alters timing of WE to allow for pre-erase loads in perpendicular  
drives.  
40  
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