ROM INTERFACE
nROMCS
nROMOE
t2
t7
t5
Note 2
t1
t3
t2
t8
t6
t3
RD[x]
SD[x]
t4
Note 1
FIGURE 13 - ROM INTERFACE TIMING
Note 1: RD[x] driven by FDC37B72x, SD[x] driven by system
Note 2: RD[x] driven by ROM, SD[x] driven by FDC37B72x
TABLE 81 - ROM INTERFACE TIMING
DESCRIPTION MIN
SD[x] Valid to RD[x] Valid
NAME
t1
TYP
MAX
25
UNITS
ns
t2
t3
t4
nROMCS Active to RD[X] Driven
nROMCS Inactive to RD[X] Float
RD[x] Valid to SD[x] Valid
25
25
25
ns
ns
ns
t5
t6
t7
t8
nROMCS Active to SD[X] Driven
nROMCS Inactive to SD[X] Float
nROMOE Active to RD[x] Float
nROMOE Inactive to RD[x] Driven
25
25
25
25
ns
ns
ns
ns
Note 1: Outputs have a 50 pf load.
208