Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features
Datasheet
Negative terminal is connected to ground
The occurrence of a fault will cause 80h to be loaded into the associated reading register, except for
the case when the negative terminal is connected to ground. A temperature reading of 80h will cause
the corresponding diode error bit to be set. This will cause the INT# pin to become active if the
individual, group (TEMP), and global enable (INTEN) bits are set.
Notes:
The individual remote diode enable bits and the TEMP bit are located in on page 69. The INTEN
bit is located in bit[2] of on page 68.
When 80h is loaded into the Remote Diode Reading Register the PWM output(s) controlled by the
zone associated with that diode input will be forced to full on. See Thermal Zones on page 27.
If the diode is disabled, the fault bit in the interrupt status register will not be set. In this case, the
occurrence of a fault will cause 00h to be loaded into the associated reading register. The limits must
be programmed accordingly to prevent unwanted fan speed changes based on this temperature
reading. If the diode is disabled and a fault condition does not exist on the diode pins, then the
associated reading register will contain a “valid” reading.
5.5
Interrupt Pin
The INT# function is used as an interrupt output for out-of-limit temperature, voltage events, and/or fan
errors.
The INT# signal can be enabled onto the PWM2 or the TACH3 pins.
To configure the PWM2/INT# pin for the interrupt function, set bit[1] P2INT of the CONF register
(7Fh) to ‘1’
To configure the TACH3/INT# pin for the interrupt function, set bit[0] T3INT of the CONF register
(7Fh) to ‘1’
To enable the interrupt pin to go active, set bit 2 of the Special Function Register (7Ch) to ‘1’.
To enable temperature event, voltage events and/or fan events onto the INT# pin:
To enable out-of-limit temperature events set bit[0] of the Interrupt Enable 3 (TEMP) register (82h)
to ‘1’.
To enable out-of-limit voltage events set bit[0] of the Interrupt Enable 1(VOLT) register (7Eh) to ‘1’
To enable Fan tachometer error events set bit[0] of the Interrupt Enable 2(Fan Tachs) register (80h)
to ‘1’.
See Figure 5.1 on page 22. The following description assumes that the interrupt enable bits for all
events are set to enable the interrupt status bits to be set.
If the internal or remote temperature reading violates the low or high temperature limits, INT# will be
forced active low (if all the corresponding enable bits are set: individual enable bits (D1_EN, D2_EN,
and/or AMB_EN), group enable bit (TEMP_EN) and the global enable bit (INTEN)). This pin will remain
low while the Internal Temp Error bit or one or both of the Remote Temp Error bits in Interrupt Status
1 Register is set and the enable bit is set.
The INT# pin will not become active low as a result of the remote diode fault bits becoming set.
However, the occurrence of a fault will cause 80h to be loaded into the associated reading register,
which will cause the corresponding diode error bit to be set. This will cause the INT# pin to become
active if enabled.
The INT# pin can be enabled to indicate out-of-limit voltages. Bit[0] of the Interrupt Enable 1(VOLT)
register (7Eh) is used to enable this option. When this bit is set, if one or more of the voltage readings
violates the low or high limits, INT# will be forced active low (if all the corresponding enable bits are
set: individual enable bits (VCC_Error_En, 12V_Error_En, 5V_Error_En, 33V_Error_En,
VCCP_Error_En, 25V_Error_En, 18V_Error_En, and/or 15V_Error_En), group enable (VOLT_EN), and
global enable (INT_EN)). This pin will remain low while the associated voltage error bit in the Interrupt
Status Register 1 or Interrupt Status Register 2 is set.
SMSC EMC6D102
Revision 0.4 (06-15-06)
DATA2S3HEET
SMSC [ SMSC CORPORATION ]
