RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Chapter 5 SMBus Slave Interface
The EMC2113 communicates with a host controller, such as an SMSC SIO, through the SMBus. The
SMBus is a two-wire serial communication protocol between a computer host and its peripheral
devices.
5.1
System Management Bus Interface Protocol
The EMC2113 contains an SMBus slave interface. A detailed timing diagram is shown in Figure 5.1,
"SMBus Timing Diagram". Stretching of the SMCLK signal is supported, however the EMC2113 will not
stretch the clock signal.
TLOW
THIGH
THD:STA
TSU:STO
TRISE
TFALL
SMCLK
TSU:STA
THD:STA
THD:DAT
TSU:DAT
SMDATA
TBUF
S
S
P
P - Stop Condition
P
S - Start Condition
Figure 5.1 SMBus Timing Diagram
5.1.1
5.1.2
SMBus Start Bit
The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic
‘0’ state while the SMBus Clock line is in a logic ‘1’ state.
SMBus Address and RD / WR Bit
The SMBus Address Byte consists of the 7-bit slave address followed by the RD / WR indicator bit. If
this RD / WR bit is a logic ‘0’, then the host device is writing data to the slave device. If this RD / WR
bit is a logic ‘1’, then the host device is reading data from the slave device.
The EMC2113 SMBus slave address is determined via the pull-up resistor connected to the
ADDR_SEL pin as shown Table 5.1, "ADDR_SEL Pin Decode".
Table 5.1 ADDR_SEL Pin Decode
PULL-UP RESISTOR VALUE
FAN CONTROL ADDRESS
4.7k Ohm ±5%
6.8k Ohm ±5%
10k Ohm ±5%
15k Ohm ±5%
0101_100(r/w)
0101_101(r/w)
0101_110(r/w)
1001_100(r/w)
SMSC EMC2113
Revision 1.2 (10-08-09)
DATA1S7HEET
SMSC [ SMSC CORPORATION ]
