Dual RPM-Based PWM Fan Controller with Hardware Thermal Shutdown
Datasheet
6.39
GPIO Output Register
Table 6.56 GPIO Output Register
ADDR
R/W
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
GPIO
Output 1
GPIO3 GPIO2 GPIO1
_OUT _OUT _OUT
E4h
-
-
-
-
-
00h
The GPIO Output Register controls the state of the corresponding GPIO pins when they areconfigured
as GPIOs and as outputs.
If the output is configured as an open-drain output, then it requires a pull-up resistor to VDD. Setting
the corresponding bit to a ‘1’ will act to disable the output allowing the pull-up resistor to pull the output
high. Setting the corresponding bit to a ‘0’ will enable the output and drive the pin to a logical ‘0’ state.
If the output is configured as a push-pull output, then output pin will immediately be driven to match
the corresponding bit setting.
6.40
GPIO Interrupt Enable Register
Table 6.57 GPIO Interrupt Enable Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
GPIO
Interrupt
Enable
GPIO3_ GPIO2_ GPIO1_
INT_EN INT_EN INT_EN
E5h
R/W
-
-
-
-
-
00h
The GPIO Interrupt Enable Register enables the GPIOs to assert the ALERT pin when they change
state. When the GPIO pins are disabled or configured as outputs, then these bits are ignored.
Bit 3 - 0 - GPIOx_INT_EN - Allows the ALERT# pin to be asserted when the GPIOx pin changes state
(when configured as an input).
‘0’ (default) - The ALERT# pin will not be asserted when the GPIOx pin changes state (when
configured as an input).
‘1’ - The ALERT# pin will be asserted when the GPIOxpin changes state (when configured as an
input).
6.41
GPIO Status Register
Table 6.58 GPIO Status Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
GPIO
Status
GPIO3_ GPIO2_ GPIO1_
STS STS STS
E6h
R-C
-
-
-
-
-
00h
The GPIO Status Register indicates which GPIO has changed states to cause the ALERT pins to be
asserted. This register is cleared when it is read. The bits in this register are set whenever the
corresponding GPIO changes states regardless if the ALERT pins are asserted. Once a bit is set, it
will remain set until read.
SMSC EMC2104
Revision 1.74 (05-08-08)
DATA8S1HEET
SMSC [ SMSC CORPORATION ]
