SMBus Fan Control with 1°C Accurate Temperature Monitoring
Datasheet
FAN_SETTING
⎛
⎝
⎞
⎠
--------------------------------------------
FAN =
× VDD
[4]
64
These values are independent of the POLARITY bit (see Section 6.16). Therefore, a value of 00h in
the Fan Setting Register will always refer to minimum output drive while a setting of 3Fh in the Fan
Setting Register will always refer to maximum output drive.
APPLICATION NOTE: The output of the DAC driver is dependent upon the current load. With a low current load,
the output will be from 0V to an LSB (approximately 52mV at VDD = 3.3V) below VDD with
a maximum of 64 linear steps.
6.19
PWM Frequency Register
Table 6.24 PWM Frequency Register
ADDR.
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
4Dh
R/W
PWM Frequency
-
-
-
PWM_F[4:0]
17h
The PWM Frequency Register determines the final PWM frequency and “effective resolution” of the
PWM driver. It has no affect on the DAC output resolution.
It is recommended that this register be set at 1Fh for maximum resolution. See Appendix A for full
operation of the PWM_F register and its interactions with the PWM Resolution and Duty Cycle
6.20
PWM Frequency Divide Register
Table 6.25 PWM Frequency Divide Register
ADDR.
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
PWM Frequency
Divide
4Eh
R/W
PWM_D[7:0]
01h
This register holds an alternate PWM Frequency divide value that can be used instead of the CLK_SEL
bit function. This register can be written at any time, however unless the CLK_OVR bit is set to a logic
‘1’, it is not used.
When the CLK_OVR bit is set to a logic ‘1’, the PWM Frequency Divide Register is used in conjunction
with the PWM Frequency Register to determine the final PWM frequency that the load will see. When
the CLK_OVR bit is set to a logic ‘0’, the setting of this register is not changed and is not used to
determine the effective PWM frequency.
The PWM frequency when the PWM Frequency Divide Register is used is shown in Equation [5].
SMSC EMC2101
Revision 2.53 (03-13-07)
DATA4S3HEET
SMSC [ SMSC CORPORATION ]
