SMBus Fan Control with 1°C Accurate Temperature Monitoring
Datasheet
Table 6.1 Register Set in Hexadecimal Order (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
R/W
REGISTER NAME
FUNCTION
PAGE
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
BFh
R/W (See
Note 6.1)
Lookup Table Temp Setting 4 Look Up Table
Temperature Setting 4
7Fh
3Fh
7Fh
3Fh
7Fh
3Fh
7Fh
3Fh
7Fh
3Fh
00h
Page 45
R/W (See
Note 6.1)
Lookup Table Fan Setting 4
Associated Fan Setting for
Temp Setting 4
Page 45
Page 45
Page 45
Page 45
Page 45
Page 45
Page 45
Page 45
Page 45
Page 46
R/W (See
Note 6.1)
Lookup Table Temp Setting 5 Look Up Table
Temperature Setting 5
R/W (See
Note 6.1)
Lookup Table Fan Setting 5
Associated Fan Setting for
Temp Setting 5
R/W (See
Note 6.1)
Lookup Table Temp Setting 6 Look Up Table
Temperature Setting 6
R/W (See
Note 6.1)
Lookup Table Fan Setting 6
Associated Fan Setting for
Temp Setting 6
R/W (See
Note 6.1)
Lookup Table Temp Setting 7 Look Up Table
Temperature Setting 7
R/W (See
Note 6.1)
Lookup Table Fan Setting 7
Associated Fan Setting for
Temp Setting 7
R/W (See
Note 6.1)
Lookup Table Temp Setting 8 Look Up Table
Temperature Setting 8
R/W (See
Note 6.1)
Lookup Table Fan Setting 8
Associated Fan Setting for
Temp Setting 8
R/W
Averaging Filter
Selects averaging function
for external diode
FDh
FEh
FFh
R
R
R
Product ID
ID
16h or 28h
5Dh
Page 47
Page 47
Page 47
Manufacturer ID
Revision Register
SMSC
REV
01h
Note 6.1 The Look Up Table Registers are made Read Only if the PWM Program bit (bit 5) in PWM
Configuration Register (4Ah) is set.
6.1
6.2
Data Read Interlock
When the External Diode High Byte Register is read, the External Diode Low byte is copied into an
internal ‘shadow’ register. The user is free to read the low byte at any time and be guaranteed that it
will correspond to the previously read high byte. Regardless if the low byte is read or not, reading from
an External Diode High Byte Register will automatically refresh this stored low byte data.
When the TACH Reading Low Byte Register is read, the TACH Reading high byte is copied into an
internal ‘shadow’ register. The user is free to read the high byte at any time and be guaranteed that it
will correspond to the previously read low byte. Regardless if the high byte is read or not, reading from
the TACH Reading Low Byte Register will automatically refresh this stored high byte data.
Register Descriptions
The registers are described in detail below. A bit entry of a ‘-’ indicates that the bit is not used and will
always read 0.
SMSC EMC2101
Revision 2.53 (03-13-07)
DATA3S1HEET
SMSC [ SMSC CORPORATION ]
