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EMC1701-1-KP-TR 参数 Datasheet PDF下载

EMC1701-1-KP-TR图片预览
型号: EMC1701-1-KP-TR
PDF下载: 下载PDF文件 查看货源
内容描述: 高边电流检测和内置1A ° C温度监控器 [High-Side Current-Sense and Internal 1°C Temperature Monitor]
分类和应用: 监控
文件页数/大小: 54 页 / 876 K
品牌: SMSC [ SMSC CORPORATION ]
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High-Side Current-Sense and Internal 1°C Temperature Monitor  
Datasheet  
4.4  
ALERT Output  
The ALERT pin is an open drain output and requires a pull-up resistor to VPULLUP and has two modes  
of operation: Interrupt mode and Comparator mode. The mode of the ALERT output is selected via  
the ALERT / COMP bit in the Configuration Register (see Section 5.5).  
The ALERT pin modes apply to the High Limit only for all channels. The Low Limits will always cause  
the ALERT pin to behave as if it were in Interrupt mode.  
The ALERT pin is used as an interrupt signal or as an SMBus Alert signal that allows an SMBus slave  
to communicate an error condition to the master. One or more SMBus Alert outputs can be hard-wired  
together.  
4.4.1  
ALERT Pin Interrupt Mode  
When configured to operate in Interrupt mode, the ALERT pin asserts low when an out-of-limit  
measurement (> high limit or < low limit) is detected on any temperature measurement and the  
consecutive alert queue has been filled.  
Additionally, the ALERT pin may be asserted if the measured current or the source voltage are out of  
limit (> high limit or < low limit).  
The ALERT pin will remain asserted as long as an out-of-limit condition remains. Once the out-of-limit  
condition has been removed, the ALERT pin will remain asserted until the appropriate status bits are  
cleared. The pin can be masked by setting the MASK_ALL bit. Once the ALERT pin has been masked,  
it will be de-asserted and remain de-asserted until the MASK_ALL bit is cleared by the user. Any  
interrupt conditions that occur while the ALERT pin is masked will update the Status Register normally.  
When the ALERT pin is configured to operate in Interrupt mode, the Peak Detector circuitry will not  
generate interrupts when a current peak is detected.  
4.4.2  
ALERT Pin Comparator Mode  
When the ALERT pin is configured to operate in Comparator mode, it will be asserted if the measured  
temperature meets or exceeds the high limit. The ALERT pin will remain asserted until the temperature  
drops below the high limit minus the Tcrit Hysteresis value (see Section 5.9).  
Additionally, the ALERT pin may be asserted if the measured current or the source voltage meet or  
exceed their respective high limit. The ALERT pin will remain asserted until the measured values drop  
below the corresponding high limit minus the Vcrit Hysteresis value (see Section 5.23).  
When the ALERT pin is asserted in Comparator mode, the corresponding high limit status bits will be  
set. Reading these bits will not clear them until the ALERT pin is deasserted. Once the ALERT pin is  
deasserted, the status bits will be automatically cleared.  
The MASK_ALL (see Section 5.5) bit will not block the ALERT pin in this mode; however, individual  
mask bits (see Section 5.10) will control the respective events that will assert the ALERT pin.  
When the ALERT pin is configured to operate in Comparator mode and the Peak Detector circuitry is  
linked to the ALERT pin, an interrupt will be generated when a current peak is detected (see  
Section 5.15).  
4.5  
THERM Output  
The THERM output is asserted independently of the ALERT output and cannot be masked. Whenever  
the measured temperature meets or exceeds the user programmed Tcrit Limit value for the  
programmed number of consecutive measurements, the THERM output is asserted. Once it has been  
asserted, it will remain asserted until the measured temperatures drops below the Tcrit Limit minus the  
Tcrit Hysteresis (also programmable).  
Additionally, the THERM pin will be asserted if the current sense Peak Detection circuitry has detected  
a current spike (see Section 4.1.4). The THERM pin will remain asserted so long as the Peak Detection  
circuitry continues to detect excessive instantaneous current (greater than the programmed threshold).  
Revision 1.2 (09-27-10)  
SMSC EMC1701  
DATA2S6HEET