1°C Multiple Temperature Sensor with Hardware Controlled Standby & Hottest of Multiple Zones
Datasheet
Chapter 4 System Management Bus Interface Protocol
4.1
System Management Bus Interface Protocol
The EMC1438 communicates with a host controller, such as an SMSC SIO, through the SMBus. The
SMBus is a two-wire serial communication protocol between a computer host and its peripheral
devices. A detailed timing diagram is shown in Figure 4.1. Stretching of the SMCLK signal is supported;
however, the EMC1438 will not stretch the clock signal.
T
T
T
T
SU:STO
LOW
HIGH
HD:STA
T
FALL
SMCLK
T
RISE
T
T
SU:DAT
SU:STA
T
HD:DAT
T
HD:STA
SMDATA
TBUF
S
S
P
P
S - Start Condition
P - Stop Condition
Figure 4.1 SMBus Timing Diagram
4.1.1
4.1.2
SMBus Start Bit
The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic
‘0’ state while the SMBus Clock line is in a logic ‘1’ state.
SMBus Address and RD / WR Bit
The SMBus Address Byte consists of the 7-bit client address followed by a 1-bit RD / WR indicator. If
this RD / WR bit is a logic ‘0’, the SMBus host is writing data to the client device. If this RD / WR bit
is a logic ‘1’, the SMBus host is reading data from the client device.
The EMC1438 SMBus address is determined by a single resistor connected between ground and the
ADDR_SEL pin, as shown in Table 4.1.
Table 4.1 ADDR_SEL Resistor Setting
RESISTOR
(+/-10%)
RESISTOR
(+/- 10%)
SMBUS ADDRESS
SMBUS ADDRESS
GND
270
1001_100(r/w)
1001_101(r/w)
1001_110(r/w)
1001_111(r/w)
1500
2700
1001_001(r/w)
1001_010(r/w)
1001_011(r/w)
0011_000(r/w)
560
5600
1000
>18000
All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information.
SMSC EMC1438
Revision 1.0 (04-29-10)
DATA1S3HEET
SMSC [ SMSC CORPORATION ]
