1°C Temperature Sensor with Beta Compensation
Datasheet
6.3
Status Register
Table 6.3 Status Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
02h
R
Status
BUSY
-
-
HIGH LOW FAULT THERM
-
00h
The Status Register reports general error conditions. To identify specific channels, refer to
Section 6.10, Section 6.15, Section 6.16, and Section 6.17. The individual Status Register bits are
cleared when the appropriate High Limit, Low Limit, or THERM Limit register has been read or cleared.
Bit 7 - BUSY - This bit indicates that the ADC is currently converting. This bit does not cause either
the ALERT or THERM pins to be asserted.
Bit 4 - HIGH - This bit is set when any of the temperature channels exceeds its programmed high limit.
See the High Limit Status Register for specific channel information (Section 6.15). When set, this bit
will assert the ALERT pin.
Bit 3 - LOW - This bit is set when any of the temperature channels drops below its programmed low
limit. See the Low Limit Status Register for specific channel information (Section 6.16). When set, this
bit will assert the ALERT pin.
Bit 2 - FAULT - This bit is asserted when a diode fault is detected on any of the external diode
channels. See the External Diode Fault Register for specific channel information (Section 6.10). When
set, this bit will assert the ALERT pin.
Bit 1 - THERM - This bit is set when the any of the temperature channels exceeds its programmed
THERM limit. See the THERM Limit Status Register for specific channel information (Section 6.17).
When set, this bit will assert the THERM pin.
6.4
Configuration Register
Table 6.4 Configuration Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
03h
09h
MASK_
ALL
RUN/
STOP
ALERT/
COMP
DAVG_
DIS
-
R/W
Configuration
RECD1
RECD2
RANGE
00h
APDD
The Configuration Register controls the basic operation of the device. This register is fully accessible
at either address.
Bit 7 - MASK_ALL - Masks the ALERT pin from asserting.
‘0’ (default) - The ALERT pin is not masked. If any of the appropriate status bits are set the ALERT
pin will be asserted.
‘1’ - The ALERT pin is masked. It will not be asserted for any interrupt condition unless it is
configured as a secondary THERM pin. The Status Registers will be updated normally.
Bit 6 - RUN / STOP - Controls Active/Standby modes.
‘0’ (default) - The device is in Active mode and converting on all channels.
‘1’ -The device is in Standby mode and not converting.
SMSC EMC1403/EMC1404
Revision 2.0 (08-10-12)
DATA3S1HEET
SMSC [ SMSC CORPORATION ]
