Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications
Datasheet
If the temperature drops below the Therm Limit or Hardware Thermal Shutdown Limit, the counter is
reset. If the programmed number of consecutive measurements exceed the Therm Limit or Hardware
Thermal Shutdown Limit, and the appropriate channel is linked to the SYS_SHDN pin, the SYS_SHDN
pin will be asserted low.
Once the SYS_SHDN pin is asserted, the consecutive Therm counter will not reset until the
corresponding temperature drops below the appropriate limit minus the corresponding hysteresis.
Bits 6-4 - CTHRM[2:0] - Determines the number of consecutive measurements that must exceed the
corresponding Therm Limit before the THERM pin is asserted. All temperature channels use this value
to set the respective counters. The consecutive Therm counter is incremented whenever any
measurement exceed the corresponding Therm Limit.
If the temperature drops below the Therm Limit, the counter is reset. If a number of consecutive
measurements above the Therm Limit occurs, the THERM pin is asserted low.
Once the THERM pin has been asserted, the consecutive therm counter will not reset until the
corresponding temperature drops below the Therm Limit minus the Therm Hysteresis value.
The bits are decoded as shown in Table 6.12. The default setting is 4 consecutive out of limit
conversions.
Bits 3-1 - CALRT[2:0] - Determine the number of consecutive measurements that must have an out of
limit condition or diode fault before the ALERT / THERM2 pin is asserted. Both temperature channels
use this value to set the respective counters. The bits are decoded as shown in Table 6.12. The default
setting is 1 consecutive out of limit conversion.
Table 6.12 Consecutive Alert / Therm Settings
NUMBER OF CONSECUTIVE OUT OF LIMIT
2
1
0
MEASUREMENTS
1
0
0
0
(default for CALRT[2:0])
0
0
0
1
1
1
2
3
4
1
1
1
(default for CTHRM[2:0])
6.12
Beta Configuration Register 25h
Table 6.13 Beta Configuration Register
ADDR.
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
External
Diode Beta
Configuration
25h
R/W
-
-
-
-
ENABLE
BETA[2:0]
08h
This register is used to set the Beta Compensation factor that is used for the external diode channel.
‘0’ - The Beta Compensation Factor auto-detection circuitry is disabled.
‘1’ (default) - The Beta Compensation factor auto-detection circuitry is enabled. At the beginning of
every conversion, the optimal Beta Compensation factor setting will be determined and applied.
Revision 1.0 (07-11-13)
34
SMSC EMC1182
DATASHEET
SMSC [ SMSC CORPORATION ]
