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EMC1001-AFZQ-TR 参数 Datasheet PDF下载

EMC1001-AFZQ-TR图片预览
型号: EMC1001-AFZQ-TR
PDF下载: 下载PDF文件 查看货源
内容描述: 1.5 ℃, SMBus的温度传感器在小型SOT- 23 [1.5∑C SMBus Temperature Sensor in Miniature SOT-23]
分类和应用: 传感器温度传感器
文件页数/大小: 16 页 / 302 K
品牌: SMSC [ SMSC CORPORATION ]
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1.5°C SMBus Temperature Sensor in Miniature SOT-23  
Datasheet  
Note 4.3 Revision number may change. Please obtain the latest version of this document from the  
SMSC web site.  
At device power-up, the default values are stored in all registers. A power-on-reset is initiated when  
power is first applied to the part and the VDD supply exceeds the POR threshold. Reads of undefined  
registers will return 00h and writes to undefined registers will be ignored.  
The EMC1001 uses an interlock mechanism that locks the low byte value when the high byte register  
is read. This prevents updates to the low byte register between high byte and low byte reads. This  
interlock mechanism requires that the high byte register always be read prior to reading the low byte  
register.  
4.7  
Status Register  
The status register is a read only register that stores the operational status of the part. When either  
TLOW or THIGH are set (TA low limit or TA > high limit) and the ALERT/THERM2 pin is not masked,  
the ALERT/THERM2 pin will assert. See Section 4.3 on page 11 for more details on the ALERT  
function.  
Table 4.4 Status Register  
STATUS REGISTER  
BIT  
NAME  
Busy  
FUNCTION  
7
6
5
4
3
2
1
0
1 when ADC is converting  
THIGH  
TLOW  
1 when Temperature High Limit is exceeded  
1 when Temperature Low Limit is exceeded  
Reserved  
Reserved  
Reserved  
Reserved  
THRM  
1 when THERM limit is exceeded  
Bit 7 indicates that the ADC is busy converting a value. Bits 6 and 5 indicate that the temperature  
measurement is above or below the limits respectively. Bit 0 indicates that the measured temperature  
has exceeded the THERM limit. When bit 0 goes high the ADDR/THERM output will be asserted.  
Each bit is cleared individually when the status register is read, provided that the error condition for  
that bit no longer exists. The ALERT/THERM2 output is latched and will not be reset until the host has  
responded with an alert response address (ARA=0001 100). The ALERT/THERM2 output will not reset  
if the status register has not been cleared.  
4.8  
Configuration Register  
The configuration register controls the functionality of the temperature measurements.  
SMSC EMC1001  
Revision 1.6 (01-29-07)  
DATA1S3HEET