10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
Chapter 8 Timing Diagrams
AD0-AD2,
VALID
VALID DATA
D3-D15
t1
t2,
t4
nCS
t3
t12
t11
ALE
nDS
t6
t7
t13
t5
t14
Note 2
t8
t9
t16
t10
DIR
t15
nIOCS16
Previous Value
Invalid
Valid Value
MUST BE: BUSTMG pin = HIGH and RBUSTMG bit = 0
Parameter
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nDS Low
min
max
units
t1
t2
t3
t4
t5
t6
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
20
10
10
10
15
40
20
nDS Low to Valid Data
0
4TARB*
10
10
20
20
60
20
0
t7 nDS High to Data High Impedance
t8 Cycle Time (nDS Low to Next Time Low)
t9 DIR Setup to nDS Active
t10 DIR Hold from nDS Inactive
t11 ALE High Width
t12 ALE Low Width
t13 nDS Low Width
t14 nDS High Width
t15 nIOCS16 Hold Delay from ALE Low
t16 nIOCS16 Output Delay from ALE Low
40
*
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Note 1: The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
Read cycle for Address Pointer Low/High Registers occurring after an access
to Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
Note 2:
Note 2 is applied to an access to Data Register by DMA transfer.
Figure 8.1 - Multiplexed Bus, 68XX-Like Control Signals; Read Cycle
Revision 02-27-06
Page 60
SMSC COM20022I 3V
DATASHEET
SMSC [ SMSC CORPORATION ]
