10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
reception of a packet (not by RESET), and since the TRI bit may easily be reset by issuing a "Clear
Receive Interrupt" command, there is no need to use the RI bit of the Interrupt Mask Register to mask
interrupts generated by the TRI bit of the Status Register. In Command Chaining mode, the "Disable
Receiver" command will cancel the oldest reception, unless the reception has already begun. If both
receptions should be canceled, two "Disable Receiver" commands should be issued.
6.8
Reset Details
6.8.1 Internal Reset Logic
The COM20022I includes special reset circuitry to guarantee smooth operation during reset. Special care
is taken to assure proper operation in a variety of systems and modes of operation. The COM20022I
contains digital filter circuitry and a Schmitt Trigger on the nRESET signal to reject glitches in order to
ensure fault-free operation.
The COM20022I supports two reset options; software and hardware reset. A software reset is generated
when a logic "1" is written to bit 7 of the Configuration Register. The device remains in reset as long as
this bit is set. The software reset does not affect the microcontroller interface modes determined after
hardware reset, nor does it affect the contents of the Address Pointer Registers, the Configuration
Register, or the Setup1 Register. A hardware reset occurs when a low signal is asserted on the nRESET
input. The minimum reset pulse width is 5TXTL. This pulse width is used by the internal digital filter, which
filters short glitches to allow only valid resets to occur.
Upon reset, the transmitter portion of the device is disabled and the internal registers assume those states
outlined in the Internal Registers section. After the nRESET signal is removed the user may write to the
internal registers. Since writing a non-zero value to the Node ID Register wakes up the COM20022I core,
the Setup1 Register should be written before the Node ID Register. Once the Node ID Register is written
to, the COM20022I reads the value and executes two write cycles to the RAM buffer. Address 0 is written
with the data D1H and address 1 is written with the Node ID. The data pattern D1H was chosen arbitrarily,
and is meant to provide assurance of proper microsequencer operation.
6.9
Initialization Sequence
6.9.1 Bus Determination
Writing to and reading from an odd address location from the COM20022I's address space causes the
COM20022I to determine the appropriate bus interface. When the COM20022I is powered on the internal
registers may be written to. Since writing a non-zero value to the Node ID Register wakes up the core, the
Setup1 Register should be written to before the Node ID Register. Until a non-zero value is placed into the
NID Register, no microcode is executed, no tokens are passed by this node, and no reconfigurations are
generated by this node. Once a non-zero value is placed in the register, the core wakes up, but the node
will not attempt to join the network until the TX Enable bit of the Configuration Register is set.
Before setting the TX Enable bit, the software may make some determinations. The software may first
observe the Receive Activity and the Token Seen bits of the Diagnostic Status Register to verify the health
of the receiver and the network.
Next, the uniqueness of the Node ID value placed in the Node ID Register is determined. The TX Enable
bit should still be a logic "0" until it is ensured that the Node ID is unique. If this node ID already exists, the
Duplicate ID bit of the Diagnostic Status Register is set after a maximum of 210mS (or 420mS if the ET1
and ET2 bits are other than 1,1). To determine if another node on the network already has this ID, the
COM20022I compares the value in the Node ID Register with the DID's of the token, and determines
whether there is a response to it. Once the Diagnostic Status Register is read, the DUPID bit is cleared.
SMSC COM20022I
Page 53
Revision 09-27-07
DATASHEET
SMSC [ SMSC CORPORATION ]
