10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
LONG PACKET
FORMAT
SHORT PACKET
FORMAT
ADDRESS
ADDRESS
0
SID
DID
SID
0
1
2
DID
1
2
3
COUNT = 256-N
0
COUNT = 512-N
NOT USED
DATA BYTE 1
DATA BYTE 2
NOT USED
COUNT
DATA BYTE 1
DATA BYTE 2
COUNT
DATA BYTE N-1
DATA BYTE N
255
511
DATA BYTE N-1
DATA BYTE N
NOT USED
511
N = DATA PACKET LENGTH
SID = SOURCE ID
DID = DESTINATION ID
(DID = 0 FOR BROADCASTS)
Figure 6.3 - RAM Buffer Packet Configuration
6.6.2 Transmit Sequence
During a transmit sequence, the microcontroller selects a 256 or 512 byte segment of the RAM buffer and
writes into it. The appropriate buffer size is specified in the "Define Configuration" command. When long
packets are enabled, the COM20022I interprets the packet as either a long or short packet, depending on
whether the buffer address 2 contains a zero or non-zero value. The format of the buffer is shown in
Figure 5.7 Address 0 contains the Source Identifier (SID); Address 1 contains the Destination Identifier
(DID); Address 2 (COUNT) contains, for short packets, the value 256-N, where N represents the number
of information bytes in the message, or for long packets, the value 0, indicating that it is indeed a long
packet. In the latter case, Address 3 (COUNT) would contain the value 512-N, where N represents the
number of information bytes in the message. The SID in Address 0 is used by the receiving node to reply
to the transmitting node. The COM20022I puts the local ID in this location, therefore it is not necessary to
write into this location. Please note that a short packet may contain between 1 and 253 data bytes, while a
long packet may contain between 257 and 508 data bytes. A minimum value of 257 exists on a long
packet so that the COUNT is expressible in eight bits. This leaves three exception packet lengths which
do not fit into either a short or long packet; packet lengths of 254, 255, or 256 bytes. If packets of these
lengths must be sent, the user must add dummy bytes to the packet in order to make the packet fit into a
long packet.
Once the packet is written into the buffer, the microcontroller awaits a logic "1" on the TA bit, indicating that a
previous transmit command has concluded and another may be issued. Each time the message is loaded
and a transmit command issued, it will take a variable amount of time before the message is transmitted,
depending on the traffic on the network and the location of the token at the time the transmit command was
issued. The conclusion of the Transmit Command will generate an interrupt if the Interrupt Mask allows it. If
the device is configured for the Command Chaining operation, please see the Command Chaining section for
further detail on the transmit sequence. Once the TA bit becomes a logic "1", the microcontroller may issue
the "Enable Transmit from Page fnn" command, which resets the TA and TMA bits to logic "0". If the
SMSC COM20022I
Page 49
Revision 09-27-07
DATASHEET
SMSC [ SMSC CORPORATION ]
