10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Table 6.13 - DMA Count Register
BIT
BIT NAME
SYMBOL
DESCRIPTION
7-0
Terminal Count
TC7-TC0
TC7-TC0: Used for non-burst or burst mode. These are the lower 8
bits of the Terminal Count setting register. The MSB (TC8) is in the
Bus Control Register. The Terminal Count setting range is from 1 to
512 counts (TC8 - TC0 all zeroes means 512 counts).
TIM7-TIM0: Used for Programmable-Burst by Timer mode. These bits
are for setting the term of the continuous DMA transfer. The time
range is from 100nS to 25.6μS. The step is 100nS (TIM7-TIM0 all
zeroes means 25.6μs).
CYC7-CYC0: Used for Programmable-Burst by Cycle mode. These
bits are for setting the term of the continuous DMA transfer. The cycle
range is from 2 to 256 cycles. CYC7-CYC0 all zeroes means 256
cycles. (1 is illegal)
Timer Mode
Cycle Mode
TIM7-TIM0
CYC7-CYC0
Data Register
I/O Address 04H
Memory
Data Bus
2K x 8
INTERNAL
RAM
8
D0-D7
Address Pointer Register
I/O Address 02H I/O Address 03H
High
Low
Memory
Address Bus
11-Bit Counter
11
Figure 6.2 - Sequential Access Operation
Revision 09-27-07
Page 46
SMSC COM20022I
DATASHEET
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