10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Table 6.2 - Write Register Summary
WRITE
ADDR
00
MSB
LSB
TA/
TTA
C0
REGISTER
INTERRUPT
MASK
NEW
RECON
RI/TR1
0
0
DMA
EXCNAK
NEXTID
END
C4
0
COMMAND
ADDRESS
PTR HIGH
ADDRESS
PTR LOW
DATA*
01
02
C7
C6
AUTO-
INC
C5
0
C3
C2
C1
A9
RD-
DATA
DMAEN
A10
A8
03
A7
A6
A5
A4
A3
A2
D2
A1
D1
A0/
SWAP
04
05
D7
D6
0
D5
0
D4
0
D3
D0
(R/W)*
(R/W)*
SUB-
AD2
SUB-
AD1
SUB-
AD0
SUB-
AD0
TID0
NID0
SUBADR
06
RESET
CCHEN
TXEN
ET1
ET2
BACK-
PLANE
TID2
SUB-
AD1
CONFIG-
URATION
TENTID
07-0
07-1
07-2
TID7
NID7
TID6
NID6
FOUR
NAKS
0
TID5
NID5
0
TID4
NID4
RCV-
ALL
TID3
NID3
CKP3
TID1
NID1
CKP1
NID2
NODEID
SETUP1
SLOW-
ARB
P1-
MODE
CKP2
07-3
07-4
0
0
0
0
0
0
0
TEST
RBUS-
TMG
0
CKUP1
CKUP0
EF
NO-
RCN-
TM1
RCN-
TM0
SETUP2
SYNC
DMA-
MD0
07-5
07-6
W16
0
ITCEN/
RTRG
TC8/
RSYN/
GTTM
TC4/
DMA-
MD1
TC-
POL
DRQ-
POL
BUS
CONTROL
TC7/
TIM7/
CYC7
TC6/
TIM6/
CYC6
TC5/
TIM5/
CYC5
TC3/
TIM3/
CYC3
TC2/
TIM2/
CYC2
TC1/
TIM1/
CYC1
TC0/
TIM0/
CYC0
DMA COUNT
TIM4/
CYC4
Note*:
This bit can be written and read.
*DATA REGISTER AT 16 BIT ACCESS
BIT
15
BIT
14
BIT
13
BIT
12
BIT
11
BIT
10
BIT
9
BIT
8
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
BIT
0
REGISTER
ADDR
D
15
D
14
D
13
D
12
D
11
D
10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA
04
6.2
Internal Registers
The COM20022I contains 16 internal registers. Table 6.1 and Table 6.2 illustrate the COM20022I register
map. All undefined bits are read as undefined and must be written as logic "0".
6.2.1 Interrupt Mask Register (IMR)
The COM20022I is capable of generating an interrupt signal when certain status bits become true. A write
to the IMR specifies which status bits will be enabled to generate an interrupt. The bit positions in the IMR
are in the same position as their corresponding status bits in the Status Register and Diagnostic Status
Register. A logic "1" in a particular position enables the corresponding interrupt. The Status bits capable of
generating an interrupt include the Receiver Inhibited bit, DMAEND bit (new to the COM20022I), New Next
Revision 09-27-07
Page 32
SMSC COM20022I
DATASHEET