10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Table 6.1 - Read Register Summary
READ
REGISTER
STATUS
MSB
LSB
TA/
TTA
X
ADDR
00
RI/TRI
X/RI
X/TA
POR
TEST
RECON
TENTID
A10
TMA
NEW
DIAG.
MY-
RECON
DUPID
RCV-
ACT
TOKEN
EXC-
NAK
01
02
03
NEXTID
STATUS
ADDRESS
PTR HIGH
ADDRESS
PTR LOW
DATA*
RD-
DATA
AUTO-
INC
X
X
DMA-
EN
A9
A1
D1
A8
A7
A6
A5
A4
A3
A2
A0/
SWAP
D7
D6
0
D5
0
D4
0
D3
D2
D0
04
05
SUB ADR
(R/W)*
(R/W)*
SUB-
AD2
SUB-
AD1
SUB-
AD0
CONFIG-
URATION
TENTID
RESET
CCHEN
TXEN
ET1
ET2
BACK-
PLANE
SUB-
AD1
SUB-
AD0
06
TID7
NID7
TID6
NID6
TID5
NID5
X
TID4
NID4
TID3
NID3
CKP3
TID2
NID2
CKP2
TID1
NID1
CKP1
TID0
NID0
07-0
07-1
07-2
NODE ID
SETUP1
P1
MODE
FOUR
NAKS
RCV-
ALL
SLOW-
ARB
NEXT ID
SETUP2
NXT
ID7
NXT
ID6
NXT
ID5
NXT
ID4
NXT
ID3
NXT
ID2
NXT
ID1
NXT
ID0
07-3
RBUS-
TMG
X
CKUP1
CKUP0
EF
NO-
SYNC
RCN-
TM1
RCM-
TM2
07-4
07-5
BUS
CONTROL
W16
X
ITCEN/
RTRG
TC8/
RSYN/
GTTM
TC4/
DMA-
MD1
DMA-
MD0
TCPOL
DRQ-
POL
DMA
COUNT
TC7/
TIM7/
CYC7
TC6/
TIM6/
CYC6
TC5/
TIM5/
CYC5
TC3/
TIM3/
CYC3
TC2/
TIM2/
CYC2
TC1/
TIM1/
CYC1
TC0/
TIM0/
CYC0
TIM4/
CYC4
07-6
Note*:
This bit can be written and read.
*DATA REGISTER AT 16 BIT ACCESS
BIT
15
BIT
14
BIT
13
BIT
12
BIT
11
BIT
10
BIT
9
BIT
8
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
BIT
0
REGISTER
DATA
ADDR
04
D
15
D
14
D
13
D
12
D
11
D
10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SMSC COM20022I
Page 31
Revision 09-27-07
DATASHEET
SMSC [ SMSC CORPORATION ]
