欢迎访问ic37.com |
会员登录 免费注册
发布采购

COM200221 参数 Datasheet PDF下载

COM200221图片预览
型号: COM200221
PDF下载: 下载PDF文件 查看货源
内容描述: 10 Mbps的ARCNET ( ANSI 878.1 )控制器2Kx8片上RAM [10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM]
分类和应用: 控制器
文件页数/大小: 82 页 / 509 K
品牌: SMSC [ SMSC CORPORATION ]
 浏览型号COM200221的Datasheet PDF文件第24页浏览型号COM200221的Datasheet PDF文件第25页浏览型号COM200221的Datasheet PDF文件第26页浏览型号COM200221的Datasheet PDF文件第27页浏览型号COM200221的Datasheet PDF文件第29页浏览型号COM200221的Datasheet PDF文件第30页浏览型号COM200221的Datasheet PDF文件第31页浏览型号COM200221的Datasheet PDF文件第32页  
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM  
Datasheet  
5.2.3 Differential Driver Configuration  
The Differential Driver Configuration is a special case of the Backplane Mode. It is a dc coupled  
configuration recommended for applications like car-area networks or other cost-sensitive applications  
which do not require direct compatibility with existing ARCNET nodes and do not require isolation. The  
Differential Driver Configuration cannot communicate directly with nodes utilizing the Traditional Hybrid  
Configuration. Like the Backplane Configuration, the Differential Driver Configuration does not isolate the  
node from the media.  
The Differential Driver interface includes a RS485 Driver/Receiver to transfer the data between the cable  
and the COM20022I. The nPULSE1 signal transmits the data, provided the Transmit Enable signal is  
active. The nPULSE1 signal issues a 200nS (at 2.5Mbps) negative pulse to transmit a logic "1". Lack of  
pulse indicates a logic "0". The RXIN signal receives the data, the transmitter portion of the COM20022I is  
disabled during reset and the nPULSE1, nPULSE2 and nTXEN pins are inactive.  
5.2.4 Programmable TXEN Polarity  
To accommodate transceivers with active high ENABLE pins, the COM20022I contains a programmable  
TXEN output. To program the TXEN pin for an active high pulse, the nPULSE2 pin should be connected  
to ground. To retain the normal active low polarity, nPULSE2 should be left open. The polarity  
determination is made at power on reset and is valid only for Backplane Mode operation. The nPULSE2  
pin should remain grounded at all times if an active high polarity is desired.  
A0  
/nM  
UX  
A1  
LE  
A2/  
BA  
ADDRESS  
DECODING  
CIRCUITRY  
2K x 8  
RAM  
nIOCS16  
ADDITIONAL  
REGISTERS  
AD0-AD2,  
D3-D15  
STATUS/  
COMMAND  
REGISTER  
nPULSE1  
nPULSE2  
nTXEN  
nINTR  
TX/RX  
LOGIC  
MICRO-  
SEQUENCER  
AND  
RXIN  
WORKING  
REGISTERS  
RESET  
LOGIC  
nRESET  
XTAL1  
XTAL2  
OSCILLATOR  
nRD/nDS  
nWR/DIR  
nCS  
BUS  
ARBITRATION  
CIRCUITRY  
DREQ  
nDACK  
NODE ID  
LOGIC  
RECONFIGURATION  
TIMER  
DMA  
TC  
nREFEX  
Figure 5.10 - Internal Block Diagram  
Revision 09-27-07  
Page 28  
SMSC COM20022I  
DATASHEET  
 复制成功!