10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
The following rough timing diagram of the non-burst mode DMA data transfer is included for illustration
purposes.
Figure 5.5 - Non-Burst Mode DMA Data Transfer Rough Timing
DREQ
nDACK
Read/Write
Signal
TC
The timing of the Burst mode DMA data transfer is found in the Timing Diagrams section of this data sheet.
The basic sequence of operation is as follows:
nDACK becomes active (low) upon DREQ becoming active (high) and catching the host bus (AEN=
“1”).
DREQ becomes inactive after TC asserts (when nDACK= “0”). In this case, DREQ doesn't become
active again after nDACK becomes inactive.
nDACK becomes inactive after DREQ= 0 and the present cycle finishes.
The following rough timing diagram of the non-burst mode DMA data transfer is included for illustration
purposes.
DREQ
nDACK
Read/Write
Signal
TC
Figure 5.6 - Burst Mode DMA Data Transfer Rough Timing
SMSC COM20022I
Page 23
Revision 09-27-07
DATASHEET
SMSC [ SMSC CORPORATION ]
