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COM20020ILJP3V 参数 Datasheet PDF下载

COM20020ILJP3V图片预览
型号: COM20020ILJP3V
PDF下载: 下载PDF文件 查看货源
内容描述: 通用局域网控制器2K ×8板载RAM [Universal Local Area Network Controller with 2K x 8 On-Board RAM]
分类和应用: 控制器局域网
文件页数/大小: 82 页 / 537 K
品牌: SMSC [ SMSC CORPORATION ]
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PROTOCOL DESCRIPTION
NETWORK PROTOCOL
Communication on the network is based on a
token passing protocol. Establishment of the
network configuration and management of the
network protocol are handled entirely by the
COM20020's internal microcoded sequencer. A
processor or intelligent peripheral transmits data
by simply loading a data packet and its destination
ID into the COM20020's internal RAM buffer, and
issuing a command to enable the transmitter.
When the COM20020 next receives the token, it
verifies that the receiving node is ready by first
transmitting a FREE BUFFER ENQUIRY
message. If the receiving node transmits an
ACKnowledge message, the data packet is
transmitted followed by a 16-bit CRC. If the
receiving node cannot accept the packet (typically
its receiver is inhibited), it transmits a Negative
AcKnowledge message and the transmitter
passes the token. Once it has been established
that the receiving node can accept the packet and
transmission is complete, the receiving node
verifies the packet. If the packet is received
successfully, the receiving node transmits an
ACKnowledge
INTERNAL
CLOCK
FREQUENCY
40 MHz
20 MHz
message (or nothing if it is not received
successfully) allowing the transmitter to set the
appropriate status bits to indicate successful or
unsuccessful delivery of the packet. An interrupt
mask permits the COM20020 to generate an
interrupt to the processor when selected status
bits become true. Figure 1 is a flow chart
illustrating the internal operation of the
COM20020 connected to a 20 MHz crystal
oscillator.
DATA RATES
The COM20020 is capable of supporting data
rates from 156.25 Kbps to 5 Mbps. The following
protocol description assumes a 5 Mbps data rate.
To attain the faster data rates, the clock frequency
may be doubled by the internal clock multiplier
(see next section). For slower data rates, an
internal clock divider scales down the clock
frequency. Thus all timeout values are scaled as
shown in the following table:
Example: IDLE LINE Timeout @ 5 Mbps = 41
μs.
IDLE LINE Timeout for 156.2 Kbps is 41
μs
* 32 =
1.3 ms
CLOCK
PRESCALER
Div. by 8
Div. by 8
Div. by 16
Div. by 32
Div. by 64
Div. by 128
DATA RATE
5 Mbps
2.5 Mbps
1.25 Mbps
625 Kbps
312.5 Kbps
156.25 Kbps
TIMEOUT SCALING
FACTOR (MULTIPLY BY)
1
2
4
8
16
32
8