5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
reset does not affect the microcontroller interface modes determined after hardware reset, nor does it affect the contents
of the Address Pointer Registers, the Configuration Register, or the Setup1 Register. A hardware reset occurs when a
low signal is asserted on the nRESET input. The minimum reset pulse width is 5TXTL. This pulse width is used by the
internal digital filter, which filters short glitches to allow only valid resets to occur.
Upon reset, the transmitter portion of the device is disabled and the internal registers assume those states outlined in the
Internal Registers section. After the nRESET signal is removed the user may write to the internal registers. Since writing
a non-zero value to the Node ID Register wakes up the COM20020I core, the Setup1 Register should be written before
the Node ID Register. Once the Node ID Register is written to, the COM20020I reads the value and executes two write
cycles to the RAM buffer. Address 0 is written with the data D1H and address 1 is written with the Node ID. The data
pattern D1H was chosen arbitrarily, and is meant to provide assurance of proper microsequencer operation.
7.5 Initialization Sequence
Bus Determination
Writing to and reading from an odd address location from the COM20020I's address space causes the COM20020I to
determine the appropriate bus interface. When the COM20020I is powered on the internal registers may be written to.
Since writing a non-zero value to the Node ID Register wakes up the core, the Setup1 Register should be written to
before the Node ID Register. Until a non-zero value is placed into the NID Register, no microcode is executed, no
tokens are passed by this node, and no reconfigurations are generated by this node. Once a non-zero value is placed in
the register, the core wakes up, but the node will not attempt to join the network until the TX Enable bit of the
Configuration Register is set.
Before setting the TX Enable bit, the software may make some determinations. The software may first observe the
Receive Activity and the Token Seen bits of the Diagnostic Status Register to verify the health of the receiver and the
network.
Next, the uniqueness of the Node ID value placed in the Node ID Register is determined. The TX Enable bit should still
be a logic "0" until it is ensured that the Node ID is unique. If this node ID already exists, the Duplicate ID bit of the
Diagnostic Status Register is set after a maximum of 420mS (or 840mS if the ET1 and ET2 bits are other than 1,1). To
determine if another node on the network already has this ID, the COM20020I compares the value in the Node ID
Register with the DID's of the token, and determines whether there is a response to it. Once the Diagnostic Status
Register is read, the DUPID bit is cleared. The user may then attempt a new ID value, wait 420mS before checking the
Duplicate ID bit, and repeat the process until a unique Node ID is found. At this point, the TX Enable bit may be set to
allow the node to join the network. Once the node joins the network, a reconfiguration occurs, as usual, thus setting the
MYRECON bit of the Diagnostic Status Register.
The Tentative ID Register may be used to build a network map of all the nodes on the network, even once the
COM20020I has joined the network. Once a value is placed in the Tentative ID Register, the COM20020I looks for a
response to a token whose DID matches the Tentative ID Register. The software can record this information and
continue placing Tentative ID values into the register to continue building the network map. A complete network map is
only valid until nodes are added to or deleted from the network. Note that a node cannot detect the existence of the next
logical node on the network when using the Tentative ID. To determine the next logical node, the software should read
the Next ID Register.
7.6 Improved Diagnostics
The COM20020I allows the user to better manage the operation of the network through the use of the internal
Diagnostic Status Register.
A high level on the My Reconfiguration (MYRECON) bit indicates that the Token Reception Timer of this node expired,
causing a reconfiguration by this node. After the Reconfiguration (RECON) bit of the Status Register interrupts the
microcontroller, the interrupt service routine will typically read the MYRECON bit of the Diagnostic Status Register.
Reading the Diagnostic Status Register resets the MYRECON bit. Successive occurrences of a logic "1" on the
MYRECON bit indicates that a problem exists with this node. At that point, the transmitter should be disabled so that the
entire network is not held down while the node is being evaluated.
The Duplicate ID (DUPID) bit is used before the node joins the network to ensure that another node with the same ID
does not exist on the network. Once it is determined that the ID in the Node ID Register is unique, the software should
write a logic "1" to bit 5 of the Configuration Register to enable the basic transmit function. This allows the node to join
the network.
Revision 12-06-06
42
SMSC COM20020I 3.3V
DATASHEET
SMSC [ SMSC CORPORATION ]
