5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
Table of Contents
Chapter 1
Chapter 2
Chapter 3
Chapter 4
4.1
General Description................................................................................................................6
Pin Configurations..................................................................................................................7
Description of Pin Functions ..................................................................................................9
Protocol Description .............................................................................................................12
Network Protocol........................................................................................................................................12
Data Rates .................................................................................................................................................12
Selecting Clock Frequencies Above 2.5 Mbps....................................................................................12
Network Reconfiguration............................................................................................................................13
Broadcast Messages..................................................................................................................................14
Extended Timeout Function .......................................................................................................................14
Response Time...................................................................................................................................14
Idle Time .............................................................................................................................................14
Reconfiguration Time..........................................................................................................................14
Line Protocol ..............................................................................................................................................14
Invitations To Transmit........................................................................................................................15
Free Buffer Enquiries ..........................................................................................................................15
Data Packets.......................................................................................................................................15
Acknowledgements.............................................................................................................................16
Negative Acknowledgements..............................................................................................................16
System Description ..............................................................................................................17
Microcontroller Interface.............................................................................................................................17
High Speed CPU Bus Timing Support ................................................................................................20
Transmission Media Interface ....................................................................................................................21
Traditional Hybrid Interface.................................................................................................................21
Backplane Configuration.....................................................................................................................21
Differential Driver Configuration ..........................................................................................................23
Programmable TXEN Polarity.............................................................................................................23
Functional Description..........................................................................................................26
Microsequencer..........................................................................................................................................26
Internal Registers.......................................................................................................................................27
Interrupt Mask Register (IMR).............................................................................................................27
Data Register ......................................................................................................................................28
Tentative ID Register ..........................................................................................................................28
Node ID Register.................................................................................................................................28
Next ID Register..................................................................................................................................28
Status Register....................................................................................................................................29
Diagnostic Status Register..................................................................................................................29
Command Register .............................................................................................................................29
Address Pointer Registers ..................................................................................................................29
4.2
4.2.1
4.3
4.4
4.5
4.5.1
4.5.2
4.5.3
4.6
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
Chapter 5
5.1
5.1.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
Chapter 6
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10
6.2.11
6.2.12
6.2.13
Configuration Register.....................................................................................................................29
Sub-Address Register .....................................................................................................................29
Setup 1 Register..............................................................................................................................30
Setup 2 Register..............................................................................................................................30
6.3
6.3.1
6.3.2
6.4
6.4.1
6.4.2
6.4.3
6.5
6.5.1
6.5.2
Internal RAM ..............................................................................................................................................40
Sequential Access Memory.................................................................................................................40
Access Speed .....................................................................................................................................40
Software Interface ......................................................................................................................................40
Selecting RAM Page Size...................................................................................................................41
Transmit Sequence.............................................................................................................................42
Receive Sequence..............................................................................................................................44
Command Chaining....................................................................................................................................45
Transmit Command Chaining .............................................................................................................45
Receive Command Chaining ..............................................................................................................46
Reset Details..............................................................................................................................................47
6.6
6.6.1
Internal Reset Logic ............................................................................................................................47
6.7
Initialization Sequence ...............................................................................................................................47
6.7.1
Bus Determination...............................................................................................................................47
SMSC COM20020I Rev D
Page 3
Revision 12-05-06
DATASHEET
SMSC [ SMSC CORPORATION ]
