5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
Chapter 4 Protocol Description
4.1
Network Protocol
Communication on the network is based on a token passing protocol. Establishment of the network
configuration and management of the network protocol are handled entirely by the COM20020ID's internal
microcoded sequencer. A processor or intelligent peripheral transmits data by simply loading a data packet
and its destination ID into the COM20020ID's internal RAM buffer, and issuing a command to enable the
transmitter. When the COM20020ID next receives the token, it verifies that the receiving node is ready by
first transmitting a FREE BUFFER ENQUIRY message. If the receiving node transmits an ACKnowledge
message, the data packet is transmitted followed by a 16-bit CRC. If the receiving node cannot accept the
packet (typically its receiver is inhibited), it transmits a Negative AcKnowledge message and the
transmitter passes the token. Once it has been established that the receiving node can accept the packet
and transmission is complete, the receiving node verifies the packet. If the packet is received
successfully, the receiving node transmits an ACKnowledge message (or nothing if it is not received
successfully) allowing the transmitter to set the appropriate status bits to indicate successful or unsuccessful
delivery of the packet. An interrupt mask permits the COM20020ID to generate an interrupt to the processor
when selected status bits become true. Figure 3.1 is a flow chart illustrating the internal operation of the
COM20020ID connected to a 20 MHz crystal oscillator.
4.2
Data Rates
The COM20020ID is capable of supporting data rates from 156.25 Kbps to 5 Mbps. The following protocol
description assumes a 5 Mbps data rate. To attain the faster data rates, the clock frequency may be
doubled by the internal clock multiplier (see next section). For slower data rates, an internal clock divider
scales down the clock frequency. Thus all timeout values are scaled as shown in the following table:
Example:
IDLE LINE Timeout @ 5 Mbps = 41 μs. IDLE LINE Timeout for 156.2 Kbps is 41 μs * 32 = 1.3 ms
INTERNAL CLOCK
TIMEOUT SCALING FACTOR
(MULTIPLY BY)
CLOCK PRESCALER
DATA RATE
FREQUENCY
40 MHz
Div. by 8
Div. by 8
5 Mbps
2.5 Mbps
1
2
20 MHz
Div. by 16
Div. by 32
Div. by 64
Div. by 128
1.25 Mbps
625 Kbps
4
8
312.5 Kbps
156.25 Kbps
16
32
4.2.1 Selecting Clock Frequencies Above 2.5 Mbps
To realize a 5 Mbps network, an external 40 MHz clock must be input. However, since 40 MHz is near the
frequency of FM radio band, it is not practical for use for noise emission reasons.
Therefore, higher frequency clocks are generated from the 20 MHz crystal as selected through two bits in
the Setup2 register, CKUP[1,0] as shown below. The selected clock is supplied to the ARCNET controller.
Revision 12-05-06
Page 12
SMSC COM20020I Rev D
DATASHEET
SMSC [ SMSC CORPORATION ]
