SYSTEM DESCRIPTION
Once the type of bus is determined,
registers.
MICROCONTROLLER INTERFACE
the COM20020-5 remains in this interface mode
until hardware reset occurs. Whenever nCS
Figures 2 and 3 illustrate typical COM20020-5
interfaces to the microcontrollers.
The
and
nRD
are
activated,
the
preset
interfaces consist of an 8-bit data bus, an
address bus, and a control bus. In order to
support a wide range of microcontrollers without
requiring glue logic and without increasing the
number of pins, the COM20020-5 automatically
detects and adapts to the type of microcontroller
being used.
determinations are assumed as final and will not
be changed until hardware reset. Refer to
Description of Pin Functions section for details
on the related signals.
All accesses to the internal RAM and the
internal registers are controlled by the
COM20020-5. The internal RAM is accessed
Upon hardware reset, the COM20020-5 first
determines whether the read and write control
signals are separate READ and WRITE signals
(like the 80XX) or DIRECTION and DATA
STROBE (like the 68XX). To determine the type
of control signals, the device requires the
software to execute at least one write access to
external memory before attempting to access
the COM20020-5. The device defaults to 80XX-
like signals. Once the type of control signals are
determined, the COM20020-5 remains in this
interface mode until the next hardware reset
occurs.
via a pointer-based scheme (refer to the
Sequential Access Memory section), and the
internal registers are accessed via direct
addressing.
Many peripherals are not fast
enough to take advantage of high-speed
microcontrollers. Since microcontrollers do not
typically have READY inputs, standard
peripherals cannot extend cycles to extend the
access time.
The access time of the
COM20020-5, on the other hand, is so fast that
it does not need to limit the speed of the
microcontroller. The COM20020-5 is designed
to be flexible so that it is independent of the
microcontroller speed.
The second determination the COM20020-5
makes is whether the bus is multiplexed or non-
multiplexed. To determine the type of bus, the
device requires the software to write to an odd
memory location followed by a read from an odd
location before attempting to access the
The COM20020-5 provides for no wait state
arbitration via direct addressing to its internal
registers and
a pointer based addressing
scheme to access its internal RAM. Note that at
the 5 Mbps data rate, the internal arbiter must
be slowed down using the SLOWARB bit of the
Setup Register. Although arbitration cycles are
slowed down, individual cycle times will still
have no wait state but the time between cycles
will lengthen. The pointer may be used in auto-
increment mode for typical sequential buffer
emptying or loading, or it can be taken out of
auto-increment mode to perform random
accesses to the RAM. The data within the RAM
COM20020-5.
The signal on the A0 pin during
tells the COM20020-5 the type
the odd access
of bus. Since multiplexed operation requires A0
to be activity on the A0 line tells the
active low,
COM20020-5 that the bus is non-multiplexed.
The device defaults to multiplexed operation.
Both
determinations
may
be
made
simultaneously by performing a WRITE followed
by a READ operation to an odd location within
is accessed through the data register.
It is
the COM20020-5 Address space
important to notice that only by writing a new
address pointer (writing to address pointer low)
COM20020-5
12
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