DESCRIPTION OF PIN FUNCTIONS
TABLE 1 - CAM35C44 PIN FUNCTION DESCRIPTION
TOTAL
BUFFER
PINS
SYMBOL
TYPE
DESCRIPTION
PROCESSOR/HOST INTERFACE (25)
8
SD[7:0]/AD[7:0]
IO12
This 8 bit bus is used to exchange
data with the host. The bus is bi-
directional and can be configured
as either an ISA system data bus
or as a multiplexed address/data
bus (TABLE 3). These pins are in
a high-impedance state when not
in the output mode.
The ISA system address bus is
used to determine the I/O address
during read and write cycles.
These two ISA system address
bus pins are general purpose I/O
pins (TABLE 30) when a
multiplexed address/data host
interface type is selected (TABLE
3).
The ISA system address bus is
used to determine the I/O address
during read and write cycles.
These three ISA system address
bus pins are memory block select
pins (TABLE 10) when a
multiplexed address/data host
interface type is selected (TABLE
3).
The active low chip select input is
a 32-byte address block decoder
when the ISA host interface type
is selected and a 256-byte page
decoder when a multiplexed
address/data host interface type is
selected (TABLE 3).
NAME
ISA System Data Bus/
Multiplexed
Address/Data Bus
(Non-ISA)
ISA System Address
Bus (SA0 - SA1)/
General Purpose I/O
4
(GPIO3 - GPIO4)
2
SA[1:0]/GPIO[4:3]
I/IO12
ISA System Address
Bus (SA2 - SA4)/
Memory Block Selects
(BS0 - BS2)
3
SA[4:2]/BS[2:0]
I
Chip Select
1
nCS
I
6
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