MULTIHOST CPU INTERFACE
The CAM35C44 multihost CPU interface is
bus with a read/write select and data strobe like
the example shown in FIGURE 5.
capable of supporting three bus configurations;
including, 1) an ISA-style address and data bus,
2) a multiplexed address/data bus with ISA-style
read/write commands like the example shown in
(FIGURE 4, and 3) a multiplexed address/data
The CPU interface type as well as the type-
specific multiplexing of the processor/host
interface pins (TABLE 1) is controlled by the
Host Interface Select pins.
FIGURE 4 - NEC UPD781C1X READ CYCLE
ADDR15-ADDR8
AB[15:8]
ADDR7-ADDR0
Data In
AB[7:0]
ADDR STB
nRD
nWR
ADDR15-ADDR8
AB[15:8]
AB[7:0]
ADDR7-ADDR0
Data In
ADDR STB
R/nW
DATA STB
FIGURE 5 - HITACHI HD63P01M1 READ CYCLE
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SMSC [ SMSC CORPORATION ]
