ARCHITECTURE
83C694D
261Ω
TPX2+
Common Mode
Choke
65Ω
TPX+
TPX-
TPX1+
Transmit
Filter
2.4ΚΩ
TPX1-
65Ω
Isolation
Transformer
Twisted Pair
Cable
TPX2-
261Ω
100 nsec
50 nsec
FIGURE 2-6. TWISTED-PAIR TRANSMIT PATH AND TIMING
The signal received from the unshielded cable can
benoisy, sominimumvoltage and timing limitsmust
An external interface circuit for TPR+ and TPR-
might be designed like Figure 2-5.
be met before the receiver logic is enabled.
A
"smart squelch"© digital noise filter is used in addi-
tion to the analog squelch circuit in the receiver.
The smart squelch circuit provides extra protection
against false collisions and false link connections.
2.7
LOOPBACK FUNCTION
When the loopback input goes high it causes the
83C694D to send serial data from the transmit data
input through the encoder, and back through the
phase-locked loop and decoder to the receive data
output. The transmit driver is in the idle state during
loopback mode and the receiver circuitry and colli-
sion detection are disabled. Loopback can be en-
abled during either AUI or TP (10BaseT) operation.
Transmit data is always looped back during TP
operation, simulating the physical broadcast char-
acteristic of 802.3 coaxial cable networks.
If the input polarity is reversed, it will be automat-
ically detected and corrected. When this happens,
the TPOL output pin will go high to signal the
controller or to turn off the polarity indicator LED.
The phase-locked loop and Manchester decoder
are the same circuits used by the AUI receiver.
Common Mode
Choke
TPR+
TP+
TP-
Receive
Filter
1 0 0 Ω 1 %
TPR-
Twisted Pair
Cable
Isolation
Transformer
FIGURE 2-5. TWISTED-PAIR RECEIVE PATH
7
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