REGISTER DESCRIPTIONS
Table 3 - COM81C17 Mode Register Description (Bits 0 - 7)
BIT
0
DESCRIPTION
CP1
- The Mode Register bit 0 determines whether the CP1 pin will be configured to provide
the function of CTS or will serve as a general purpose 1 bit input port. In either case, its
state will be reflected in Status Register bit 0.
0
→
nCP1 = CTS
1
→
nCP1 = GP INPUT
CP2 I/O
- The Mode Register bit 1 determines whether the CP2 pin will be configured as a
general purpose 1 bit output port or will serve as a general
purpose 1 bit input port. When used as an input, its state is reflected in the
Status Register bit 1. When used as an output, it’s state is controlled by the processor via
the Control Register bit 1.
0
→
nCP2 = OUTPUT
1
→
nCP2 = INPUT
CP2
- The mode register bit 2 determines whether the nCP2 pin will be configured to provide
the function of RTS or will serve as a general purpose 1 bit output port.
0
→
nCP2 = RTS
1
→
nCP2 = GP OUTPUT
CLOCK SELECT
- The Mode Register bit 3 determines whether the internal Baud Rate
Generator will supply the TX and RX clocks or the clock on the clock pin will be used as a
16X clock. The Baud Rate Select Register contents will be bypassed when an external 16X
clock is used.
0 = INTERNAL CLOCK
1 = EXTERNAL CLOCK (16X)
PARITY ENABLE
- The Mode Register bit 4 determines whether parity generation and
checking will be enabled.
0 = PARITY DISABLE
1 = PARITY ENABLE
PARITY
- The Mode Register bit 5 determines whether odd or even parity will be generated
and checked.
0 = EVEN PARITY
1 = ODD PARITY
NUMBER OF DATA BITS
- The Mode Register bit 6 determines the number of data bit that
will be presented in each data character (i.e. 7 or 8)
0 = 7BITS PER CHARACTER
1 = 8 BITS PER CHARACTER
STOP BITS
- The Mode Register bit 7 determines how many stop bits will trail
each data unit (i.e. 1 or 2)
0 = 1 STOP BIT
1 = 2 STOP BITS
A data frame will consist of a start bit, 7 or 8 data bits, an optional parity bit, and 1 or 2 stop
bits.
1
2
3
4
5
6
7
8
SMSC [ SMSC CORPORATION ]
