Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency
could cause an EOI or ISR Read to precede an IRQ transition that it should have followed. This could
cause a system fault. The host interrupt controller is responsible for ensuring that these latency issues
are mitigated. The recommended solution is to delay EOIs and ISR Reads to the interrupt controller by
the same amount as the IRQSER Cycle latency in order to ensure that these events do not occur out
of order.
AC/DC Specification Issue
All IRQSER agents must drive/sample IRQSER synchronously related to the rising edge of the PCI bus
clock. IRQSER (SIRQ) pin uses the electrical specification of the PCI bus. Electrical parameters will
follow the PCI specification section 4, sustained tri-state.
Reset and Initialization
The IRQSER bus uses nPCIRST as its reset signal (nPCIRST is equivalent to using nRESET_OUT)
and follows the PCI bus reset mechanism. The IRQSER pin is tri-stated by all agents while nPCIRST
is active. With reset, IRQSER slaves and bridges are put into the (continuous) Idle mode. The host
controller is responsible for starting the initial IRQSER cycle to collect system’s IRQ/Data default values.
The system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for
subsequent IRQSER cycles. It is the host controller’s responsibility to provide the default values to the
8259’s and other system logic before the first IRQSER cycle is performed. For IRQSER system
suspend, insertion, or removal application, the host controller should be programmed into Continuous
(IDLE) mode first. This is to guarantee IRQSER bus is in Idle state before the system configuration
changes.
Revision 1.1 (01-14-03)
274
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
