Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Table 25.2 IRQSER Sampling Periods
IRQSER PERIOD
SIGNAL SAMPLED
# OF CLOCKS PAST START
1
2
Not Used
IRQ1
2
5
3
nSMI/IRQ2
IRQ3
8
4
11
14
17
20
23
26
29
32
35
38
41
44
47
5
IRQ4
6
IRQ5
7
IRQ6
8
IRQ7
9
IRQ8
10
11
12
13
14
15
16
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
The SIRQ data frame will now support IRQ2 from a logical device; previously IRQSER Period 3 was
reserved for use by the System Management Interrupt (nSMI). When using Period 3 for IRQ2, the user
should mask off the LPC47N350’s SMI via the ESMI Mask Register. Likewise, when using Period 3 for
nSMI, the user should not configure any logical devices as using IRQ2.
IRQSER Period 14 is used to transfer IRQ13. Logical devices 4 (Ser Port), 6 (RTC), and 7 (KBD) will
have IRQ13 as a choice for their primary interrupt.
Stop Cycle Control
Once all IRQ/Data Frames have completed, the host controller will terminate IRQSER activity by
initiating a Stop Frame. Only the host controller can initiate the Stop Frame. A Stop Frame is indicated
when the IRQSER is low for two or three clocks. If the Stop Frame’s low time is two clocks, then the
next IRQSER cycle’s sampled mode is the Quiet mode; and any IRQSER device may initiate a Start
Frame in the second clock or more after the rising edge of the Stop Frame’s pulse. If the Stop Frame’s
low time is three clocks, then the next IRQSER cycle’s sampled mode is the continuous mode, and only
the host controller may initiate a Start Frame in the second clock or more after the rising edge of the
Stop Frame’s pulse.
Latency
Latency for IRQ/Data updates over the IRQSER bus in bridge-less systems with the minimum IRQ/Data
Frames of seventeen will range up to 96 clocks (3.84µS with a 25 MHz PCI Bus or 2.88µs with a 33
MHz PCI Bus). If one or more PCI to PCI Bridge is added to a system, the latency for IRQ/Data updates
from the secondary or tertiary buses will be a few clocks longer for synchronous buses, and
approximately double for asynchronous buses.
EOI/ISR Read Latency
SMSC LPC47N350
273
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
