Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
25.1
SERIRQ Mode Bit Function
Table 25.1 SERIRQ_EN Configuration Control
CR25 BIT[2]
NAME
DESCRIPTION
0
1
SERIRQ_EN
Serial IRQ Disabled
Serial IRQ Enabled (Default)
IRQSER Cycle Control
There are two modes of operation for the IRQSER Start Frame:
1. Quiet (Active) Mode
Any device may initiate a Start Frame by driving the IRQSER low for one clock, while the IRQSER is
Idle. After driving low for one clock, the IRQSER must immediately be tri-stated without at any time
driving high. A Start Frame may not be initiated while the IRQSER is active. The IRQSER is Idle
between Stop and Start Frames. The IRQSER is active between Start and Stop Frames. This mode of
operation allows the IRQSER to be Idle when there are no IRQ/Data transitions which should be most
of the time.
Once a Start Frame has been initiated, the host controller will take over driving the IRQSER low in the
next clock and will continue driving the IRQSER low for a programmable period of three to seven clocks.
This makes a total low pulse width of four to eight clocks. Finally, the host controller will drive the
IRQSER back high for one clock then tri-state.
Any IRQSER Device (i.e., The LPC47N350) which detects any transition on an IRQ/Data line for which
it is responsible must initiate a Start Frame in order to update the host controller unless the IRQSER is
already in an IRQSER Cycle and the IRQ/Data transition can be delivered in that IRQSER Cycle.
2. Continuous (Idle) Mode
Only the Host controller can initiate a Start Frame to update IRQ/Data line information. All other
IRQSER agents become passive and may not initiate a Start Frame. IRQSER will be driven low for four
to eight clocks by host controller. This mode has two functions. It can be used to stop or idle the
IRQSER or the host controller can operate IRQSER in a continuous mode by initiating a Start Frame at
the end of every Stop Frame.
An IRQSER mode transition can only occur during the Stop Frame. Upon reset, IRQSER bus is
defaulted to continuous mode, therefore only the host controller can initiate the first Start Frame. Slaves
must continuously sample the Stop Frames pulse width to determine the next IRQSER Cycle’s mode.
IRQSER Data Frame
Once a Start Frame has been initiated, the LPC47N350 will watch for the rising edge of the Start Pulse
and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample phase,
Recovery phase, and Turn-around phase. During the sample phase, the LPC47N350 must drive the
IRQSER (SIRQ pin) low, if and only if, its last detected IRQ/Data value was low. If its detected IRQ/Data
value is high, IRQSER must be left tri-stated. During the recovery phase, the LPC47N350 must drive
the SERIRQ high, if and only if, it had driven the IRQSER low during the previous sample phase. During
the turn-around phase, the LPC47N350 must tri-state the SERIRQ. The LPC47N350 drives the IRQSER
line low at the appropriate sample point if its associated IRQ/Data line is low, regardless of which device
initiated the start frame.
The Sample phase for each IRQ/Data follows the low to high transition of the Start Frame pulse by a
number of clocks equal to the IRQ/Data Frame times three, minus one, e.g. the IRQ5 Sample clock is
the sixth IRQ/Data Frame, then the sample phase is {(6 x 3) - 1 = 17} the seventeenth clock after the
rising edge of the Start Pulse.
Revision 1.1 (01-14-03)
272
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
