Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
MASTER
TARGET
PCICLK
PCICLOCKGENERATOR
(CentralResource)
SMSCI/O
nCLKRUN
Figure 24.1 CLKRUN# System Implementation Example
SERIRQ MODE
(Bit 2 of CR25)
nCLKRUN
DRIVEN BY
LPC47N252 STOPS
DRIVING
LPC47N252
ANY IRQ CHANGE o
FOR nLDRQ or IRQ
nCLKRUN FOR
nLDRQ or IRQ (after
two rising edges of
PCI_CLK)
1,2
DRQ ASSERTION
nCLKRUN
PCI_CLK
2 CLKS MIN.
Figure 24.2 Clock Start Illustration
Notes:
1. The signal “ANY IRQ CHANGE or DRQ ASSERTION” is the same as “CHANGE/ASSERTION” in
Table 24.1.
2. The LPC47N350 must continually monitor the state of CLKRUN# to maintain the PCI Clock until an
active “any IRQ change” condition has been transferred to the host in a Serial IRQ cycle. For
example, if “any IRQ change or DRQ assertion” is asserted before CLKRUN# is de-asserted (not
shown in Figure 24.2), the LPC47N350 must assert CLKRUN# as needed until the Serial IRQ cycle
has completed.
Revision 1.1 (01-14-03)
270
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
