Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Chapter 24 PCI Clock Run Support
24.1
Overview
The LPC47N350 supports the PCI CLKRUN# signal. CLKRUN# is used to indicate the PCI clock status
as well as to request that a stopped clock be started. See Figure 24.1, an example of a typical system
implementation using CLKRUN#.
CLKRUN# support is required because the LPC47N350 interrupt interface relies entirely on Serial IRQs
and PCI clock is required to drive the SER_IRQ signal (see Section 25.1, "SERIRQ Mode Bit Function").
The LPC47N350 SerIRQ Mode control is in bit D2 of the Device Mode register CR25 (see Section 27.3,
"Chip-Level (Global) Control/Configuration Registers [0x00-0x2F]"]. When the SerIRQ Mode bit is ‘0’,
Serial IRQs are disabled and the CLKRUN# pin is disabled. When the SerIRQ Mode bit is ‘1’, Serial
IRQs are enabled, the CLKRUN# pin is enabled, and the CLKRUN# support related to nLDRQ as
described in the section below is enabled.
24.2
Using CLKRUN#
The CLKRUN# pin is an open drain output and input. Refer to the PCI Mobile Design Guide Rev 1.0
for a description of the CLKRUN# function. If CLKRUN# is sampled “high”, the PCI clock is stopped or
stopping. If CLKRUN# is sampled “low”, the PCI clock is starting or started (running). CLKRUN# in the
LPC47N350 supports Serial IRQ.
24.2.1 CLKRUN# Support for Serial IRQ Cycle
If a device in the LPC47N350 asserts or de-asserts an interrupt and CLKRUN# is sampled “high”, the
LPC47N350 can request the restoration of the clock by asserting the CLKRUN# signal asynchronously
(Table 24.1). The LPC47N350 holds CLKRUN# low until it detects two rising edges of the clock. After
the second clock edge, the LPC47N350 must disable the open drain driver (Figure 24.2).
The LPC47N350 must not assert CLKRUN# if it is already driven low by the central resource; i.e., the
PCI CLOCK GENERATOR in Figure 24.1. The LPC47N350 will not assert CLKRUN# under any
conditions if the Serial IRQs are disabled.
The LPC47N350 must not assert CLKRUN# unless the line has been deasserted for two successive
clocks; i.e., before the clock was stopped (Figure 24.2).
Table 24.1 LPC47N350 CLKRUN# Function
SIRQ_MODE
(BIT 2 OF CR25)
INTERNAL INTERRUPT
CLKRUN#
ACTION
0
1
X
X
X
0
1
None
NO CHANGE
CHANGE/ASSERTION
Assert CLKRUN#
Note:
“Change” means either-edge change on any or all parallel IRQs routed to the Serial IRQ block.
“Assertion” means assertion of DMA request by a device in the LPC47N350. The “change” detection
logic must run asynchronously to the PCI Clock and regardless of the Serial IRQ mode; i.e., “continuous”
or “quiet”.
SMSC LPC47N350
269
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
