DESCRIPTION OF PIN FUNCTIONS
BUFFER
QFP/
TQFP
PIN NO.
TYPE
NAME
Drive 2
SYMBOL
DESCRIPTION
94
DRV2
I
In PS/2 mode, this input indicates whether a
second drive is connected; DRV2 should be
low if a second drive is connected. This
status is reflected in a read of Status
Register A.
Address X
nADRX
OD24
Active low address decode out: used to
decode a 1, 8, or 16 byte address block. (An
external pull-up is required). Refer to
Configuration registers CR03, CR08 and
CR09 for more information. This pin has a
30ua internal pull-up. The interrupt request
from a logical device or IRQIN may be
output on IRQ_B. Refer to the configuration
registers for more information.
Interrupt
Request B
IRQ_B
024
(If EPP or ECP Mode is enabled, this output
is pulsed low, then released to allow sharing
of interrupts.)
(OD24)
23
58
IRQIN
I
This pin is used to steer an interrupt signal
from an external device onto one of eight
IRQ outputs IRQA-H.
PWRGD
I
This active high input indicates that the
power (VCC) is valid. For device operation,
PWRGD must be active. When PWRGD is
inactive, all inputs to Mercury are
disconnected and put into a low power
mode; all outputs are put into high
impedance. The contents of all registers are
preserved as long as VCC has a valid value.
The driver current drain in this mode drops
to ISTBY - standby current. This input has
an internal 30ua pull-up.
nGAMECS
This is the Game Port Chip Select output -
active low. It will go active when the I/O
address, qualified by AEN, matches that
selected in Configuration register CR1E.
O4
98
I/O Power
No Connect
NC
14
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