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SL74LV00 参数 Datasheet PDF下载

SL74LV00图片预览
型号: SL74LV00
PDF下载: 下载PDF文件 查看货源
内容描述: 全2输入与非门 [QUAN 2-INPUT NAND GATE]
分类和应用: 输入元件
文件页数/大小: 4 页 / 42 K
品牌: SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
 浏览型号SL74LV00的Datasheet PDF文件第1页浏览型号SL74LV00的Datasheet PDF文件第2页浏览型号SL74LV00的Datasheet PDF文件第3页  
SL74LV00  
AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tLH = tHL = 6.0 ns, V =0V, V =VCC)  
IL  
IH  
Symbol  
Parameter  
Guaranteed Limit  
Unit  
VCC  
V
25°C  
-40°C ÷ 85°C  
-40°C ÷ 125°C  
min  
max  
min  
max  
min  
max  
tTHL, (tTLH  
)
)
Output Transition  
Time, Any Output  
(Figure 1)  
1.2  
2.0  
*
-
-
60  
16  
10  
-
-
-
75  
20  
13  
-
-
-
90  
24  
15  
ns  
tPHL, (tPLH  
Propagation Delay,  
Input A to Output Y  
(Figure 1)  
1.2  
2.0  
*
-
-
-
135  
23  
14  
-
-
-
405  
28  
18  
-
-
-
405  
34  
21  
CI  
Input Capacitance  
3.0  
-
7.0  
-
-
-
-
pF  
pF  
CPD  
Power Dissipation Capacitance (Per Inverter)  
ÒÀ=25°Ñ, V =0V÷VCC  
I
44  
* - VCC= (3.3±0.3) V  
Used to determine the no-load dynamic power consumption:  
PD = CPDVCC2fI+ (CLVCC2fo), fI-input frequency, fo- output frequency (MHz)  
(CLVCC2fo) – sum of the outputs  
tHL  
t
L H  
VC C  
0.9  
0.9  
V
1
Input À, B  
V
1
0.1  
0.1  
GND  
t
tP HL  
P
LH  
VC  
C
0.9  
0.9  
Output Y  
V
V
1
1
0.1  
0.1  
tT LH  
GND  
t
T HL  
V1 = 0.5 VCC  
Figure 1. Switching Waveforms  
VC C  
VI  
VO  
DEVICE  
UNDER  
TEST  
PULSE  
GENERATOR  
Termination resistance RT -  
should be equal to ZOUT pulse  
generators  
RT  
RL  
CL  
Figure 2. Test Circuit  
System Logic  
Semiconductor  
SLS  
4