SL74HC595
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
Tsu
Parameter
V
25 °C to
-55°C
£85°C
£125°C
Unit
ns
Minimum Setup Time,Serial Data
Input A to Shift Clock (Figure 5)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
Tsu
Minimum Setup Time, Shift Clock to
Latch Clock (Figure 6)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
ns
ns
ns
ns
ns
ns
th
Minimum Hold Time, Shift Clock to
Serial Data Input A (Figure 5)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
Trec
Tw
Tw
Tw
tr, tf
Minimum Recovery Time, Reset
Inactive to Shift Clock (Figure 2)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
Minimum Pulse Width, Reset (Figure
2)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
Minimum Pulse Width, Shift Clock
(Figure 1)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
Minimum Pulse Width, Latch Clock
(Figure 6)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
System Logic
Semiconductor
SLS
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
