SL74HC533
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
25 °C to £85°C
-55°C
£125°C
Unit
ns
tPLH, tPHL Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
2.0
4.5
6.0
175
35
220
44
265
53
45
30
37
tPLH, tPHL Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
ns
ns
ns
tPLZ, tPHZ Maximum Propagation Delay , Output Enable to Q
(Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
tPZL, tPZH Maximum Propagation Delay , Output Enable to Q
(Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
CIN
Maximum Input Capacitance
-
-
10
15
10
15
10
15
pF
pF
COUT
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
Power Dissipation Capacitance (Per Latch)
Typical @25°C,VCC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption:
37
pF
PD=CPDVCC2f+ICCVCC
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
tsu
Parameter
V
25 °C to -55°C
£85°C
£125°C
Unit
ns
Minimum Setup Time, Input D to
Latch Enable (Figure 4)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
th
Minimum Hold Time, Latch Enable to
Input D(Figure 4)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
ns
ns
tw
Minimum Pulse Width, Latch Enable
(Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
System Logic
Semiconductor
SLS
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
