SL74HC323
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
fmax
Parameter
V
25 °C to
-55°C
£85
°C
£125
°C
Unit
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 5)
2.0
4.5
6.0
5.0
25
29
4.0
20
24
3.4
17
20
MHz
tPLH, tPHL Maximum Propagation Delay, Clock to QA’ or QH’
(Figures 1 and 5)
2.0
4.5
6.0
170
34
29
215
43
37
255
51
43
ns
ns
ns
ns
ns
ns
tPLH, tPHL Maximum Propagation Delay, Clock to QA or QH
(Figures 1 and 5)
2.0
4.5
6.0
160
32
27
200
40
34
240
48
41
tPLZ, tPHZ Maximum Propagation Delay , OE1, OE2, S1, or S2
to QA thru QH (Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
tPZL, tPZH Maximum Propagation Delay , OE1, OE2, S1, or S2
to QA thru QH (Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
tTLH, tTHL Maximum Output Transition Time, QA thru QH
(Figures 1 and 5)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
tTLH, tTHL Maximum Output Transition Time, QA’ or QH’
(Figures 1 and 5)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
CIN
Maximum Input Capacitance
-
-
10
15
10
15
10
15
pF
pF
COUT
Maximum Three-State Output Capacitance
(Output in High-Impedance State), QA thru QH
Power Dissipation Capacitance (Per Package),
Outputs Enable
Typical @25°C,VCC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption:
240
pF
PD=CPDVCC2f+ICCVCC
System Logic
SLS
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
