SL74HC175
Quad D Flip-Flop with
Common Clock and Reset
High-Performance Silicon-Gate CMOS
The SL74HC175 is identical in pinout to the LS/ALS175. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of four D flip-flops with common Reset and
Clock inputs, and separate
D inputs. Reset (active-low) is
asynchronous and occurs when a low level is applied to the Reset
input. Information at a D input is transferred to the corresponding Q
output on the next positive-going edge of the Clock input.
ORDERING INFORMATION
SL74HC175N Plastic
SL74HC175D SOIC
TA = -55° to 125° C for all packages
·
·
·
·
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Clock
X
Outputs
Reset
L
D
X
H
L
Q
L
H
L
Q
PIN 16=VCC
PIN 8 = GND
H
L
H
H
H
H
L
X
no change
X = Don’t care
System Logic
Semiconductor
SLS
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
