SL74HC166
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
fmax
Parameter
V
25 °C to £85°C
-55°C
£125°C
Unit
Minimum Clock Frequency (50% Duty Cycle)
(Figures 2 and 4)
2.0
4.5
6.0
6.0
31
36
5.0
25
28
4.2
21
25
MHz
tPLH, tPHL Maximum Propagation Delay, Clock (or Clock
Inhibit) to QH (Figures 2,3 and 4)
2.0
4.5
6.0
140
28
24
175
35
30
210
42
36
ns
ns
ns
pF
tPHL
Maximum Propagation Delay , Clear to QH (Figures
1 and 4)
2.0
4.5
6.0
150
30
26
200
40
34
230
48
40
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
4.5
6.0
75
16
14
95
20
18
110
25
20
CIN
Maximum Input Capacitance
-
10
10
10
Power Dissipation Capacitance (Per Package)
Typical @25°C,VCC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption:
140
pF
PD=CPDVCC2f+ICCVCC
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
tsu
Parameter
V
25 °C to
-55°C
£85°C
£125°C
Unit
ns
Minimum Setup Time, Shift/Load to
Clock (Figure 3)
2.0
4.5
6.0
80
16
14
100
20
18
120
24
20
tsu
Minimum Setup Time, Data before
Clock (or Clock Inhibit) (Figure 3)
2.0
4.5
6.0
80
16
14
100
20
18
120
24
20
ns
ns
tw
Minimum Pulse Width, Clock (or
Clock Inhibit) (Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
System Logic
Semiconductor
SLS
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
