SL74HC165
8-Bit Serial or Parallel-Input/
Serial-Output Shift Register
High-Performance Silicon-Gate CMOS
The SL74HC165 is identical in pinout to the LS/ALS165. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device is an 8-bit shift register with complementary outputs
from the last stage. Data may be loaded into the register either in
parallel or in serial form. When the Serial Shift/ Parallel Load input is
low, the data is loaded asynchronously in parallel. When the Serial
Shift/Parallel Load input is high, the data is loaded serially on the rising
edge of either Clock or Clock Inhibit (see the Function Table).
The 2-input NOR clock may be used either by combining two
independent clock sources or by designating one of the clock inputs to
act as a clock inhibit.
ORDERING INFORMATION
SL74HC165N Plastic
SL74HC165D SOIC
TA = -55° to 125° C for all packages
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Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 16=VCC
PIN 8 = GND
FUNCTION TABLE
Inputs
Clock
Internal Stages
Output
QH
Operation
Serial Shift/
Clock
SA A-H
QA
QB-QG
Parallel Load
Inhibit
L
H
H
H
X
L
L
X
L
a...h
X
a
L
H
b-g
h
Asynchronous Parallel Load
Serial Shift via Clock
QAn-QFn
QAn-QFn
QGn
QGn
H
X
H
H
L
L
L
X
X
L
QAn-QFn
QAn-QFn
QGn
QGn
Serial Shift via Clock
Inhibit
H
H
H
H
X
H
L
H
X
L
X
X
X
X
X
X
no change
Inhibited Clock
H
no change
No Clock
X = Don’ t Care
QAn-QFn = Data shifted from the preceding stage
System Logic
SLS
Semiconductor
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
