SL74HC112
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
fmax
Parameter
V
25 °C to £85°C £125°C
-55°C
Unit
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
tPLH, tPHL Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
ns
ns
ns
pF
tPLH, tPHL Maximum Propagation Delay , Reset to Q or Q
(Figures 2 and 4)
2.0
4.5
6.0
155
31
26
195
39
33
235
47
40
tPLH, tPHL Maximum Propagation Delay ,Set to Q or Q (Figures
2 and 4)
2.0
4.5
6.0
165
33
28
205
41
35
250
50
43
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
CIN
Maximum Input Capacitance
-
10
10
10
Power Dissipation Capacitance (Per Flip-Flop)
Typical @25°C,VCC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption: PD=CPDVCC2f+ICCVCC
35
pF
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
tSU
Parameter
V
25 °C to-55°C
£85°C
£125°C
Unit
ns
Minimum Setup Time,J or K to
Clock (Figure 3)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
th
trec
tw
Minimum Hold Time, Clock to
J or K (Figure 3)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
ns
ns
ns
ns
Minimum Recovery Time, Set
or Reset Inactive to Clock
(Figure 2)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
Minimum Pulse Width, Clock
(Figure 1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
tw
Minimum Pulse Width, Set or
Reset (Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
tr, tf
Maximum Input Rise and Fall
Times (Figure 1)
2.0
4.5
1000
500
1000
500
1000
500
System Logic
Semiconductor
SLS
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
